Self Aligned Contact Formation via Unified Etching
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in forming high-aspect-ratio contact plugs with low yield due to the complexity and conductivity issues caused by barrier layers between upper and lower contact structures, which are formed in different steps.
Innovation Solution
A method involving multiple photolithography processes to form self-aligned contacts, allowing precise control of contact size and simultaneous formation of contacts corresponding to both source/drain regions and metal gates, thereby reducing manufacturing steps and eliminating the need for a separate 0th metal layer and lower contact structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the upper contact structure (M0) and lower contact structure are formed in different steps, then the manufacturing process can be completed, but a barrier layer will exist between the structures, affecting conductivity and increasing process complexity
Solution Approach 1:
The patent merges the formation of upper contact structure (M0) and lower contact structure into a single simultaneous etching step. By using a unified photomask pattern that defines both M0 regions and contact plug regions, both structures are created in one process operation, eliminating the barrier layer that would otherwise be deposited between separately-formed structures, thereby maintaining continuous conductivity paths.
Solution Approach 2:
The patent employs a universal etching process that simultaneously creates both M0 contact structures and lower contact plugs. The single etching step serves multiple functions: defining M0 patterns, creating contact openings, and establishing electrical connections, all without requiring separate barrier layer deposition steps for each structure type.
2Ease of manufacture
If the upper contact structure (M0) and lower contact structure are formed in different steps, then the manufacturing process can be completed, but the process complexity increases
Solution Approach 1:
The patent combines multiple manufacturing steps into a single unified etching operation. Instead of separately forming M0 structures and contact plugs with distinct process sequences, both structures are created simultaneously through one etching step guided by a unified photomask, thereby reducing the total number of process steps and simplifying the manufacturing workflow.
Solution Approach 2:
The patent uses a pre-designed unified photomask that contains all necessary pattern information for both M0 structures and contact plugs before the etching process begins. This preliminary pattern definition ensures that both structures are correctly formed in the single etching step without requiring intermediate patterning operations or additional mask alignment steps.
3Ease of manufacture
If multiple separate processes are used to form contact structures, then complete contact formation is achieved, but the yield of high aspect ratio contact plugs decreases
Solution Approach 1:
The patent merges the formation processes of M0 structures and contact plugs into a single etching operation. This unified approach ensures that both structures are created under identical process conditions with the same etch parameters, maintaining consistent etch quality and avoiding the yield losses associated with multiple separate high-aspect-ratio etching steps.
Solution Approach 2:
The unified photomask design inherently defines the precise locations and dimensions of both M0 structures and contact plugs. The self-aligned nature of the single etching process ensures that contact openings are automatically positioned correctly relative to M0 structures without requiring additional alignment steps, thereby improving yield by eliminating misalignment defects.
Data Source
AI summary
The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.