Self-Aligned Contact for Vertical FET Using Dielectric Cap
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Solution Overview
Problem
Conventional VFET architectures face challenges in scaling beyond the 7 nm node due to limitations in bottom source/drain contact-to-fin spacing and gate contact-to-fin spacing, which restricts the overall scaling factor and prevents the achievement of sub-5 nm devices, as there are no known techniques for forming self-aligned contacts in VFETs.
Innovation Solution
The method involves forming a dielectric cap over a recessed top source/drain metallization layer in VFETs, allowing for self-aligned contacts and reducing the spacing requirements between source/drain and gate contacts, thereby enabling more compact and efficient transistor design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional VFET architecture is used without self-aligned contacts, then manufacturing process is simpler, but contact-to-fin spacing requirements increase device area and restrict scaling
Solution Approach 1:
The method forms a dielectric cap over the top source/drain metallization layer before forming the bottom source/drain contact and gate contact. This preliminary action creates a self-aligned reference structure that defines the contact positions, eliminating the need for large spacing margins while maintaining manufacturing feasibility through a sequential process flow.
Solution Approach 2:
The dielectric cap serves as an intermediary structure between the top source/drain metallization layer and the bottom source/drain contact. This intermediary element enables precise alignment of the bottom contact with the source/drain region while providing electrical isolation, thereby reducing the contact-to-fin spacing requirement without compromising manufacturing simplicity.
2Productivity
If contact-to-fin spacing is reduced for scaling, then device density increases, but risk of short between contacts and metallization layer increases
Solution Approach 1:
The dielectric cap acts as an intermediary insulating layer positioned between the bottom source/drain contact and the top source/drain metallization layer. This intermediary structure provides electrical isolation that prevents shorts even when the contact-to-fin spacing is reduced for scaling, while still allowing the contact to be self-aligned to the source/drain region.
Solution Approach 2:
The solution moves the isolation function from the lateral dimension (contact-to-fin spacing) to the vertical dimension (dielectric cap thickness). By providing electrical isolation through the vertical stacking of the dielectric cap, the design can reduce lateral spacing without increasing short risk, thereby improving device density while maintaining reliability.
3Area of stationary object
If self-aligned contacts are implemented with dielectric cap, then contact-to-fin spacing is reduced, but manufacturing process complexity increases
Solution Approach 1:
The dielectric cap is formed as a preliminary structure before contact formation, serving as a self-aligned template that defines contact positions. This preliminary action integrates the alignment function into an existing process step, reducing the need for additional alignment-critical steps and thereby limiting the increase in manufacturing complexity.
4Length of moving object
If VFET scaling is pursued beyond 7 nm node, then transistor performance improves, but contact spacing requirements prevent achievement of sub-5 nm devices
Solution Approach 1:
The dielectric cap is formed in advance as a self-aligned reference structure that defines the precise position of bottom source/drain contacts and gate contacts. This preliminary alignment structure enables the contact-to-fin spacing to be reduced to dimensions compatible with sub-5 nm transistor scaling, removing the area penalty that previously constrained further scaling.
Solution Approach 2:
The invention transitions from lateral alignment methods to vertical stacking, where the dielectric cap provides alignment and isolation in the vertical dimension. This dimensional shift enables much smaller lateral contact-to-fin spacing, facilitating transistor scaling to sub-5 nm nodes while maintaining reliable contact formation.
Data Source
AI summary
Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer.