Self-Aligned Contact Features Using Dielectric Voids

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Solution Overview

Problem

The increased functional density in semiconductor devices, resulting from smaller geometry sizes, complicates the formation of contact features and increases the likelihood of shorting due to reduced distances between adjacent conductive features.

Innovation Solution

A method of forming contact features through a void in a dielectric layer, where the void is created by adjusting deposition conditions to exceed the limits of patterning processes, allowing for self-aligned contact holes that can be filled with conductive material, thereby reducing the critical dimension beyond the limitations of photolithography.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the distance between adjacent conductive features is decreased to increase functional density, then the number of interconnected conductive features per chip area increases, but the distance between contact features decreases which significantly increases the possibility of shorting the contact features

Engineering Contradiction:
Improvefunctional densityVSAvoidcontact feature shorting risk
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from two-dimensional planar contact feature formation to three-dimensional vertical alignment using void structures. By creating voids that extend vertically through dielectric layers and using them as alignment templates for contact holes, the invention enables precise positioning in the vertical dimension while maintaining reduced horizontal spacing between contact features, thus preventing shorts while achieving high functional density

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If the critical dimension of contact features is reduced to achieve higher device density, then more contact features can be formed per chip area, but the patterning process reaches its limits and cannot form features smaller than a certain size

Engineering Contradiction:
Improvecontact feature critical dimensionVSAvoidpatterning process capability
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent introduces void structures as intermediary elements that serve as alignment templates and spacing定义 structures. These voids, formed by deposition processes rather than direct patterning, act as mediators that define the critical dimensions of contact features indirectly, bypassing the limitations of photolithography patterning capabilities while achieving sub-patterning-limit dimensions

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention changes the formation mechanism from photolithography-based patterning to deposition-based void formation followed by self-aligned etching. By adjusting deposition parameters (such as conformal coverage, void nucleation conditions, and fill ratios), the critical dimension of contact features can be precisely controlled below the photolithography resolution limit, transforming the manufacturing approach to overcome equipment limitations

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables successful formation of contact features without shorting, even at close spacings, by using a void to align and fill contact holes with conductive material, reducing the risk of electrical shorts and improving manufacturing efficiency.

Implementation Method 1

allowing for self-aligned contact holes that can be filled with conductive material

Methodology Applied
Scientific EffectSelf-alignment:

Implementation Method 2

the void is created by adjusting deposition conditions to exceed the limits of patterning processes

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS11935786B2Contact features of semiconductor devices
Publication Date: 2024.03.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11935786B2 patent drawing
  • US11935786B2 patent drawing
  • US11935786B2 patent drawing

AI summary

A method of fabricating a semiconductor device includes recessing an upper portion of a first dielectric layer disposed over a conductive feature. The method includes filling the recessed upper portion with a second dielectric layer to form a void embedded in the second dielectric layer. The method includes etching the second dielectric layer and the first dielectric layer to form a contact opening that exposes at least a portion of the conductive feature using the void to vertically align at least a lower portion of the contact opening with the conductive feature. The method includes filling the contact opening with a conductive material to form a contact feature electrically coupled to the conductive feature.