Self-Aligned Contacts for 3D Logic and Memory Stacks
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Solution Overview
Problem
The challenge in semiconductor manufacturing is achieving effective 3D integration of logic devices, where scaling transistor density is hindered by limitations in contacted gate pitch and wire pitch scaling due to manufacturing variability and electrostatic device limitations, making it difficult to increase transistor density in volume rather than area.
Innovation Solution
A self-aligned process flow is developed to form contacts on stair-cased devices, decoupling dimensions from lithography resolution and overlay control, using monolithically integrated stacks of transistors with staircase configurations of dielectric and conductive layers, and isolation caps to enable vertical connections in 3D integrated logic or memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D integration is implemented to increase transistor density in volume, then transistor density is improved, but manufacturing precision deteriorates due to lithography resolution and overlay control limitations
Solution Approach 1:
The patent implements self-aligned contact formation where the contact holes are automatically positioned using the local interconnect structures themselves as alignment references. The side walls of the local interconnects serve as natural masks and alignment guides, eliminating the need for separate lithography alignment steps and overlay control, thus resolving the manufacturing precision deterioration while maintaining high transistor density in 3D integrated structures
Solution Approach 2:
The patent transitions from planar 2D contact formation to 3D vertical contact formation. Contact holes are formed vertically through dielectric layers to reach local interconnects at different elevation levels. This dimensional transition allows contacts to be formed without relying on lithographic overlay between layers, as the vertical etching process naturally aligns contacts with the underlying local interconnect structures, thereby improving transistor density without sacrificing manufacturing precision
2Quantity of substance
If contacted gate pitch is reduced to increase transistor density, then transistor density is improved, but reliability deteriorates due to electrostatic device limitations
Solution Approach 1:
The patent moves transistor stacking from 2D planar arrangement to 3D vertical stacking. Multiple transistor levels are stacked vertically with each level having its own local interconnects. This vertical arrangement increases transistor density in volume while maintaining adequate gate pitch within each level, preserving electrostatic device performance and reliability by not compressing the gate pitch below acceptable limits
Solution Approach 2:
The patent divides the transistor structure into multiple discrete levels or stages stacked vertically. Each level contains complete transistor stacks with source, drain, and gate regions. This segmentation allows each transistor level to maintain optimal dimensional proportions for electrostatic performance while the overall structure achieves high density through vertical multiplication of these segmented units
Data Source
AI summary
A semiconductor device includes dielectric layers and local interconnects that are stacked over a substrate alternatively, and extend along a top surface of the substrate laterally. Sidewalls of the dielectric layers and sidewalls of the local interconnects have a staircase configuration. The local interconnects are spaced apart from each other by dielectric layers and have uncovered portions by the dielectric layers. The semiconductor device also includes conductive layers selectively positioned over the uncovered portions of the local interconnects, where sidewalls of the conductive layers and sidewalls of the local interconnects are coplanar. The semiconductor device further includes isolation caps that extend from the dielectric layers. The isolation caps are positioned along sidewalls of the conductive layers and sidewalls of the local interconnects so as to separate the conductive layers from one another.