Self-Aligned Source/Drain Contacts Without CESL Etch Damage
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Solution Overview
Problem
The self-aligned contact (SAC) process in semiconductor device fabrication faces challenges such as etching attacks on gate hard masks and sidewall spacers, as well as risks to epitaxial source/drain bodies and gate spacers, particularly during contact etch stop layer formation, which affect device performance and reliability.
Innovation Solution
A method involving direct etching of a metal layer over source/drain bodies with a reversed tone mask, eliminating the need for a contact etch stop layer and allowing closer, wider source/drain contacts, and using metals like Ru or Mo for etch contrast with oxide-based and nitride-based hard masks, thereby reducing the risk of gate-to-contact shorting and enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional SAC process is used with contact etch stop layer, then self-aligned contact formation is achieved, but etching attacks gate hard mask and sidewall spacer causing device reliability issues
Solution Approach 1:
The patent extracts and removes the contact etch stop layer (CESL) from the conventional SAC process flow. By eliminating this intermediate layer, the process simplifies to direct etching of the metal layer over source/drain bodies, avoiding the etching attacks that occur during CESL formation while maintaining self-alignment through the metal layer's etch contrast with oxide-based and nitride-based hard masks and gate spacers.
Solution Approach 2:
The patent inverts the conventional approach by etching the metal layer directly instead of etching through multiple dielectric layers with a CESL. This reversal of the etching sequence eliminates the harmful etching attacks on gate structures while achieving the same self-aligned contact formation objective.
2Manufacturing precision
If contact etch stop layer is formed on source/drain bodies, then etching selectivity is improved, but source/drain contact width is reduced and contact-to-channel spacing increases
Solution Approach 1:
By removing the contact etch stop layer, the patent enables direct etching of the metal layer, which allows source/drain contacts to be formed with increased width dimension and positioned closer to the channel, improving electrical performance without relying on the CESL for etching selectivity.
Solution Approach 2:
The patent changes the etching parameters by directly etching the metal layer with reversed or inverse tone mask, which enables broader contact width and closer spacing to the channel while maintaining adequate selectivity through the inherent etch contrast between metal and dielectric materials.
3Manufacturing precision
If conventional SAC process is used, then multi-layer structure provides etching selectivity, but process complexity and risk of gate-to-contact shorting increase
Solution Approach 1:
The patent removes the contact etch stop layer and simplifies the process to direct metal layer etching, reducing the number of process steps and structures while maintaining etching selectivity through the metal layer's inherent contrast with surrounding materials, thereby reducing gate-to-contact shorting risk.
Solution Approach 2:
The patent merges the contact formation process into a single direct etching step of the metal layer, combining what was previously separate steps (CESL formation, CESL etching, contact opening) into one integrated process, reducing overall complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables robust self-aligned source/drain contact formation, improving electrical performance by allowing closer and wider contacts, reducing the risk of gate hard mask and spacer loss, and facilitating the integration of buried wiring lines with lower resistance and increased cross-section without occupying additional space.
Implementation Method 1
Typical metals suitable for source/drain contacts (e.g. Ru or Mo) may provide an etch contrast with respect to both oxide-based and nitride-based hard mask and gate spacers.
Data Source
AI summary
The disclosure relates to a method for forming a semiconductor device. The method includes: forming a device structure on a substrate, the device structure including a fin structure including a pair of source/drain bodies and a channel region between the pair of source/drain bodies, the channel region including at least one channel layer, and the device structure further including a gate structure extending across the channel region of the fin structure. The method also includes forming a metal layer over the source/drain bodies, etching the metal layer to define respective source/drain contacts on the source/drain bodies, and depositing an interlayer dielectric layer over the gate structure and the source/drain contacts.