Self-Aligned Source/Drain Contacts Without CESL Etch Damage
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Solution Overview
Problem
The self-aligned contact (SAC) process in semiconductor device fabrication faces challenges such as etching attacks on gate hard masks and sidewall spacers, especially during high aspect ratio contact opening etching, as well as risks to epitaxial source/drain bodies and gate spacers.
Innovation Solution
A method for forming self-aligned source/drain contacts by directly etching a metal layer over the source/drain bodies, using a mask with a reversed tone, which provides an advantageous etch contrast with oxide- and nitride-based hard masks and gate spacers, thereby avoiding the need for a contact etch stop layer and allowing closer and wider contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional SAC process is used to etch contact openings, then contact openings can be formed, but etching attacks gate hard mask and sidewall spacer
Solution Approach 1:
The patent inverts the conventional SAC approach by forming contact openings directly in the metal layer instead of etching through dielectric layers. This reversal eliminates the need for a CESL and prevents etching attacks on gate structures, as the metal layer etching does not affect underlying gate hard mask or sidewall spacer
Solution Approach 2:
The patent extracts and removes the CESL layer from the process flow entirely. By forming contact openings directly in the metal layer, the contact etch stop layer becomes unnecessary, simplifying the process and eliminating potential attack points on gate structures
2Manufacturing precision
If CESL is formed on source/drain bodies, then etching selectivity is improved, but process complexity increases and contact width is reduced
Solution Approach 1:
The patent removes the CESL layer from the process, forming contact openings directly in the metal layer. This extraction simplifies the process by eliminating an additional layer deposition and etching step, while maintaining etching selectivity through the metal layer's inherent properties
Solution Approach 2:
Instead of etching through dielectric layers with a CESL, the patent inverts the approach by etching the metal layer directly. This allows contact openings to be formed with greater width and closer spacing, improving electrical performance while reducing process complexity
3Measurement precision
If contact openings with high aspect ratio are etched, then contact alignment is achieved, but etching attacks gate structures more severely
Solution Approach 1:
The patent inverts the etching target from dielectric layers to the metal layer itself. This allows contact openings to be formed with optimal dimensions for alignment while the etching process selectively removes metal without attacking underlying gate hard mask or sidewall spacer structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the robustness against gate hard mask and gate spacer loss, allows for closer and wider source/drain contact formation, improving electrical performance, and reduces the risk of contact shorting.
Implementation Method 1
Typical metals suitable for source/drain contacts (e.g. Ru or Mo) may provide an advantageous etch contrast with respect to both oxide- and nitride-based hard mask and gate spacers.
Data Source
Figure 1a~1d
Figure 2a~2b
Figure 2c~2d
AI summary
The disclosure relates to a method for forming a semiconductor device, the method comprising: forming a device structure on a substrate, the device structure comprising a fin structure comprising a pair of source/drain bodies and a channel region between the pair of source/drain bodies, the channel region comprising at least one channel layer, and the device structure further comprising a gate structure extending across the channel region of the fin structure; forming a metal layer over the source/drain bodies; etching the metal layer to define respective source/drain contacts on the source/drain bodies; and depositing an interlayer dielectric layer over the gate structure and the source/drain contacts.