Variable Width Metal Lines with Self-Aligned Continuity Cuts
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Solution Overview
Problem
Conventional self-aligned multiple patterning techniques struggle to achieve variable line widths and pitches, particularly at minimum pitches of 38 nm or less, leading to lithographic variability and issues with continuity cuts in semiconductor interconnect systems, which can result in electrical shorting and premature failure of signal lines.
Innovation Solution
A method involving a semiconductor structure with mandrel layers and refill layers to form metal lines with variable widths and lengths, using self-aligned continuity cuts that are fully aligned with the metal lines, allowing for pitches and cuts larger than the minimum line pitch, thereby reducing lithographic variability and preventing electrical shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional self-aligned multiple patterning techniques are used to form metal lines, then the manufacturing process is relatively simple, but the manufacturing precision deteriorates at minimum pitches of 38 nm or less, leading to lithographic variability
Solution Approach 1:
The patent segments the patterning process into multiple distinct stages: forming mandrels at a first pitch, depositing spacers, selectively removing portions, and forming continuity cuts. This segmentation allows each stage to be optimized independently, achieving precise variable pitch and line width control without the limitations of conventional single-step SAMP processes at 38 nm and below
Solution Approach 2:
The patent performs preliminary actions by first forming mandrels with specific patterns, then depositing spacers that define the final metal line positions. The continuity cuts are also prepared in advance through selective removal of spacer material before final metal deposition, ensuring precise alignment and preventing lithographic variability in the final interconnect structure
2Adaptability or versatility
If variable line widths are implemented in metal lines, then the adaptability of the interconnect system improves, but the manufacturing precision deteriorates due to difficulty in achieving both variable pitch and variable line width simultaneously
Solution Approach 1:
The patent applies local quality by enabling different line widths and pitches in different regions of the interconnect system. Power lines can be made wider with larger pitch while signal lines maintain smaller dimensions, with each region's geometry independently controlled through selective spacer removal and continuity cut placement, achieving high adaptability without sacrificing manufacturing precision
Solution Approach 2:
The patent introduces dynamics by making the interconnect geometry adjustable through the spacer removal process. The continuity cuts and variable pitch sections are created by selectively removing spacer material at different locations, allowing the final metal line configuration to be dynamically adapted to different functional requirements while maintaining precise control through the self-aligned spacer formation process
3Adaptability or versatility
If continuity cuts are lithographically patterned at small pitches, then the functionality of the interconnect system improves, but the reliability deteriorates due to lithographic misalignment and overlay issues
Solution Approach 1:
The patent applies self-service by using the spacer structures themselves to define the precise locations of continuity cuts. The spacers are formed with self-aligned precision relative to the mandrels, and selective removal of spacer portions automatically positions the continuity cuts with nanometer-scale accuracy, eliminating the need for separate lithographic alignment steps and ensuring reliable electrical connections even at small pitches
Solution Approach 2:
The patent transitions from two-dimensional lithographic patterning to three-dimensional self-aligned spacer formation. The continuity cuts are defined by the vertical spacer structures rather than lateral lithographic patterns, adding a vertical dimension to the patterning process that provides inherent alignment precision and eliminates overlay errors that plague conventional lithographic approaches at small pitches
4Area of stationary object
If the spaces between metal lines become too narrow, then the area utilization improves, but the reliability deteriorates due to time delayed shorting between lines
Solution Approach 1:
The patent addresses the TDDB issue by moving from lateral space optimization to vertical spacer-based positioning. The spacer height and selective removal allow precise control of metal line positions without being constrained by minimum lateral spacing requirements, enabling narrow effective pitches while maintaining sufficient dielectric thickness and electrical insulation reliability to prevent time delayed shorting
Data Source
AI summary
A method includes providing a semiconductor structure having a mandrel layer and a hardmask layer disposed above a dielectric layer. A mandrel cell is patterned into the mandrel layer. An opening is etched into the hardmask layer. The opening is self-aligned with a sidewall of the mandrel. A refill layer is disposed over the structure and recessed down to a level that is below a top surface of the hardmask layer to form an opening plug that covers a bottom of the opening. The mandrel cell is utilized to form a metal line cell into the dielectric layer, the metal line cell having metal lines and a minimum line cell pitch. The opening plug is utilized to form a continuity cut in a metal line of the metal line cell. The continuity cut has a length that is larger than the minimum line cell pitch.