Self-Aligned FinFET Contacts Using Copper Germanide to Cut Resistance
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Solution Overview
Problem
Challenges arise during the scaling-down process of semiconductor devices, affecting quality, yield, performance, and reliability, particularly due to issues with contact resistance and complexity.
Innovation Solution
The design incorporates a semiconductor device with a gate structure comprising a gate dielectric layer, gate bottom and top conductive layers, and a gate capping layer, along with impurity regions and contacts formed of copper germanide, which reduces contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact structures are used during scaling-down, then manufacturing complexity increases, but contact resistance reduction is insufficient
Solution Approach 1:
The contact structure is divided into multiple segments: a lower contact portion extending into the semiconductor substrate, an intermediate contact portion, and an upper contact portion. This segmentation allows each portion to be optimized for its specific function (electrical connection, structural support, and reduced resistance) while maintaining manufacturability through standardized formation processes.
Solution Approach 2:
The contact structure transitions from a conventional planar contact to a multi-level three-dimensional structure with varying widths at different heights. The contact portions have different cross-sectional areas, creating a tapered geometry that reduces contact resistance by increasing the effective contact area with the substrate while maintaining alignment with the gate structure.
2Reliability
If contact area is increased to reduce resistance, then contact structure complexity increases
Solution Approach 1:
Instead of increasing contact area in the planar dimension, the invention utilizes the vertical dimension by creating a tapered contact structure where the width varies with height. The lower contact portion has a larger width than the upper contact portion, effectively increasing the contact area with the substrate without requiring a larger lateral footprint that would complicate the overall device layout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of copper germanide as conductive covering layers improves semiconductor device performance and reduces energy consumption by minimizing contact resistance.
Implementation Method 1
conductive covering layers correspondingly positioned on the contacts... the contacts comprise: lower portions correspondingly positioned on the impurity regions, middle portions correspondingly positioned on the lower portions, and upper portions correspondingly positioned on the middle portions
Data Source
AI summary
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a fin; a gate structure positioned on the fin, wherein the gate structure includes a gate dielectric layer, a gate bottom conductive layer, a gate top conductive layer, and a gate capping layer; impurity regions positioned on two sides of the fin; contacts correspondingly positioned on the impurity regions; and conductive covering layers correspondingly positioned on the contacts; wherein the contacts include lower portions correspondingly positioned on the impurity regions, middle portions correspondingly positioned on the lower portions, and upper portions correspondingly positioned on the middle portions.