Self-Aligned Coupling Gate Layout for Split-Gate Memory Scaling
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Solution Overview
Problem
There is a need to scale down the size of non-volatile memory cells while maintaining performance, simplify processing steps, and reduce operational voltages and power consumption in semiconductor devices with split-gate memory cells.
Innovation Solution
A semiconductor device with a self-aligned coupling gate structure, comprising a floating gate, a select gate, and a coupling gate insulated by a uniform thickness oxide layer, allowing for precise capacitive coupling and reduced operational voltages, and a method of forming and operating such memory cells with fewer masking steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional memory cell structures are used, then memory cell size is larger, but device density and scalability are reduced
Solution Approach 1:
The coupling gate is positioned to wrap around the floating gate structure, with portions adjacent to and over the floating gate, creating a nested configuration that maximizes space utilization and enhances capacitive coupling without increasing footprint area
Solution Approach 2:
The coupling gate extends in multiple spatial dimensions, with portions at different heights relative to the floating gate, utilizing vertical dimensionality to achieve enhanced coupling while maintaining planar footprint for high density
2Manufacturing precision
If precise gate alignment is achieved through self-alignment, then manufacturing precision is improved, but processing complexity increases
Solution Approach 1:
The coupling gate is formed using self-alignment to the floating gate, where the floating gate structure itself serves as the alignment reference, eliminating the need for separate alignment steps and reducing processing complexity while maintaining high precision
3Manufacturing precision
If uniform thickness insulation layer is used, then manufacturing precision is improved, but operational voltage requirements increase
Solution Approach 1:
The coupling gate structure utilizes localized capacitive coupling regions with specific insulation thicknesses optimized for different functional requirements, allowing low voltage operation in coupled regions while maintaining manufacturing precision through controlled local properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables smaller memory cell dimensions, reduced operational voltages, and lower manufacturing costs, with enhanced read, erase, and program performance through self-aligned gates and silicide enhancement.
Implementation Method 1
a coupling gate having a first portion disposed over and insulated from the source region and laterally adjacent to a side surface of the floating gate, and a second portion disposed over and insulated from an upper surface of the floating gate
Data Source
AI summary
A semiconductor device that comprises source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, and a coupling gate having a first portion disposed over the source region and laterally adjacent to a side surface of the floating gate, and a second portion disposed over an upper surface of the floating gate. The coupling gate is insulated from the source region and from the floating gate by an insulation layer having a uniform thickness between the first portion of the coupling gate and the source region, the first portion of the coupling gate and the side surface of the floating gate, and the second portion of the coupling gate and the upper surface of the floating gate.