Self-Aligned Cross-Grid Vertical Memory Array
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Solution Overview
Problem
Current solid state memory devices, such as RRAM and DRAM, require multiple electronic circuit elements per memory bit, leading to significant chip real estate consumption and limiting memory density due to the need for independent source and drain address lines.
Innovation Solution
A fully self-aligned cross-grid vertical memory array is developed, featuring vertical field effect transistors with self-aligned address lines and programmable elements, allowing for a compact and scalable memory architecture by integrating memory elements and access transistors in a vertical configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple electronic circuit elements are used per memory bit, then memory functionality is achieved, but chip area consumption increases
Solution Approach 1:
The patent transitions from planar memory architecture to vertical memory architecture by stacking transistor bodies vertically above the substrate. This dimensional change allows memory cells to utilize the third dimension (height), significantly reducing the footprint area required per memory bit while maintaining all necessary circuit functionality.
Solution Approach 2:
The patent merges multiple functions into shared structures: word lines are formed by gate electrodes that serve both as transistor gates and as address lines; bit lines are formed by source/drain regions that serve dual purposes. This merging reduces the total number of independent components needed, thereby reducing overall chip area consumption.
2Ease of operation
If independent source and drain address lines are provided, then memory access is enabled, but device complexity increases
Solution Approach 1:
The patent implements multi-functionality where gate electrodes serve dual roles as both transistor gates for channel control and as word lines for memory addressing. Similarly, source and drain regions serve both as current paths and as bit line connections. This universality eliminates the need for separate independent address lines, reducing device complexity while maintaining full memory access capability.
3Quantity of substance
If vertical transistor configuration is used, then memory density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning actions where mandrel structures are formed first, followed by spacer deposition that automatically defines precise widths and positions of transistor bodies, gates, and contacts. This preliminary structuring with self-aligned processes ensures high manufacturing precision is achieved through process design rather than relying solely on advanced lithography capabilities.
Data Source
AI summary
A programmable array including a plurality of cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, the transistor including a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region and includes a width dimension equivalent to a width dimension of the body of the transistor. A method of forming an integrated circuit including forming bodies in a plurality rows on a substrate, each of the bodies including a programmable element and a first diffusion region, a second diffusion region and a channel of a transistor; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material; and replacing the masking material with an address line material.