Self-aligned cross-point memory via two-step lithography
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Solution Overview
Problem
Current semiconductor fabrication techniques for cross-point memory arrays require three lithography steps, including a sub-resolution overlay, which is complex and inefficient, and there is a need for devices that utilize self-assembly molecular switching elements.
Innovation Solution
A method is described that uses two lithography steps to create cross-point structures with self-aligned connectors formed at the intersection of two conductor levels, eliminating the need for sub-resolution overlay and allowing for the integration of standard silicon processing techniques, using materials like polysilicon and metal conductors for the connectors and conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If three lithography steps including sub-resolution overlay are used to fabricate cross-point memory arrays, then the fabrication process can create the required structures, but the process complexity increases and efficiency decreases
Solution Approach 1:
The patent applies self-aligned fabrication where the connector material automatically forms at the intersection of conductor patterns without requiring additional alignment steps. The process uses self-aligned etching where the connector material serves as its own etch mask, eliminating the need for sub-resolution overlay and reducing the lithography steps from three to two while maintaining manufacturing precision
Solution Approach 2:
The patent segments the fabrication process into distinct material deposition and etching steps. By depositing connector material that is selectively etchable relative to conductor materials, the process separates the formation of different structure components into independent steps, allowing simpler lithography patterns to define multiple features through selective etching
2Ease of manufacture
If standard silicon processing techniques are integrated into the fabrication process, then the ease of manufacture improves, but the process requires new materials and methods unlike traditional approaches
Solution Approach 1:
The patent employs composite material structures where conductor materials (such as tungsten or copper) are combined with connector materials (such as polysilicon or silicide) that have selective etchability. This composite approach allows the use of standard silicon processing techniques like CVD and PECVD while enabling self-aligned fabrication through the differential etching properties of the material组合
Solution Approach 2:
The patent changes the etch selectivity parameter by selecting connector materials with different etch rates compared to conductor materials. By controlling the etch selectivity through material selection and process conditions, the patent enables self-aligned etching where the connector material is removed selectively to form vias and contacts without affecting the conductor patterns
Data Source
AI summary
Fabricating a cross-point memory structure using two lithography steps with a top conductor and connector or memory element and a bottom conductor orthogonal to the top connector. A first lithography step followed by a series of depositions and etching steps patterns a first channel having a bottom conductor. A second lithography step followed by a series of depositions and etching steps patterns a second channel orthogonal to the first channel and having a memory element connecting the an upper conductor and the lower conductor at their overlaid intersections.