Self-Aligned Cross Point Resistor Memory Array Fabrication
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Solution Overview
Problem
Prior art cross point resistor memory arrays suffer from potential cross-talk between adjacent bits due to the etching of colossal magnetoresistance (CMR) memory material using the top electrode as a mask, leading to interference during programming processes.
Innovation Solution
A method for fabricating a self-aligned, multi-level cross point resistor memory array using a silicon substrate with ion implantation, deposition of electrodes and sacrificial layers, and smoothing with CMP to maintain isolation and prevent cross-talk, incorporating high-quality single crystalline silicon P/N junctions for upper level memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If CMR memory material is etched using top electrode as a mask, then the fabrication process is simplified, but cross-talk between adjacent bits occurs leading to interference during programming
Solution Approach 1:
The patent divides the CMR memory material into isolated regions separated by trenches. Each bit cell's CMR material is physically segmented from adjacent bits by etching trenches through the CMR layer and filling with insulator material, eliminating cross-talk while maintaining fabrication simplicity through self-aligned processes.
Solution Approach 2:
The patent introduces an insulator material as an intermediary substance filled into the trenches between adjacent CMR material regions. This insulator acts as a mediator that electrically isolates adjacent bits, preventing interference during programming while allowing the top electrode to continue serving as the etch mask.
2Quantity of substance
If multi-level memory array is fabricated, then memory density is increased, but fabrication complexity and leakage current increase
Solution Approach 1:
The patent extends the memory structure from two-dimensional to three-dimensional by stacking multiple levels of CMR material and electrodes vertically. Each level is separated by isolation trenches and insulator layers, enabling increased memory density while maintaining self-aligned fabrication processes that manage complexity.
Solution Approach 2:
The patent implements nested structures where multiple CMR material layers are stacked vertically with electrodes and isolation structures nested between them. Each level is contained within the overall structure with proper isolation, allowing high-density multi-level memory while managing fabrication through repeated application of the same self-aligned processes.
3Reliability
If isolation trenches are etched through CMR material, then cross-talk is prevented, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary patterning of the top electrode and hard mask layers before etching the isolation trenches. The top electrode serves as a pre-positioned mask that defines the trench locations, ensuring precise alignment with the CMR material regions and reducing manufacturing precision requirements for the subsequent trench etching step.
Solution Approach 2:
The patent employs self-aligned processes where previously deposited layers (top electrode, hard mask) automatically serve as alignment references for subsequent etching steps. The etch process uses these existing layers as masks, eliminating the need for separate alignment operations and reducing precision requirements while ensuring accurate trench placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a completely isolated, high-performance, self-aligned cross point resistor memory array with minimized cross-talk, enabling efficient programming and reduced leakage current, suitable for large-scale, high-density memory applications.
Implementation Method 1
Each bit has its own P/N junction diode to isolate adjacent bits
Implementation Method 2
implanting ions into the silicon substrate to form a top P+ layer and a buried N+ layer
Implementation Method 3
A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses
Data Source
AI summary
A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.