Self-Aligned Dielectric Gate Walls and Plugs for Nanowire Scaling
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Solution Overview
Problem
The challenge of scaling multi-gate and nanowire transistors is exacerbated by the trade-off between critical dimension and spacing, leading to constraints in lithographic processes, particularly in forming gate-end-to-end plugs with high aspect ratios.
Innovation Solution
The implementation of a self-aligned dielectric gate wall and plug structure, where the dielectric gate wall is aligned symmetrically with the nanowires, reducing the aspect ratio requirement for gate plug etching and eliminating the need for precise lithographic alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithographic processes are used to pattern transistor features, then critical dimension scaling is achieved, but spacing between features becomes constrained
Solution Approach 1:
The patent applies preliminary action by forming gate plugs and dielectric walls before final transistor patterning. The gate plugs are positioned in advance with relaxed alignment requirements, and dielectric walls are formed to define precise feature locations later, enabling aggressive scaling without compromising spacing control
Solution Approach 2:
The patent introduces dielectric walls as intermediary structures that mediate between the gate plugs and the final transistor features. These dielectric walls serve as self-aligned masks and structural guides, enabling precise feature definition while decoupling the critical dimension scaling from lithographic spacing constraints
2Length of stationary object
If gate plug etching is performed with high aspect ratios, then vertical gate structure is achieved, but manufacturing complexity and precision requirements increase
Solution Approach 1:
The patent employs asymmetric structure formation where dielectric walls are formed only in specific regions adjacent to the gate plugs, creating self-aligned reference structures that guide subsequent etching processes. This asymmetry provides built-in alignment features that reduce the complexity of high aspect ratio gate plug etching
Solution Approach 2:
The dielectric walls serve as self-aligned masks and structural guides that automatically define the positions and dimensions of gate plugs. The walls are formed from the same material layers as the gate plugs, enabling self-aligned etching processes that eliminate the need for separate alignment steps and reduce manufacturing precision requirements
3Manufacturing precision
If precise lithographic alignment is required for gate-end-to-end plugs, then feature positioning accuracy is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent implements self-aligned fabrication where dielectric walls and gate plugs are formed using the same material layers and etching processes. The dielectric walls automatically serve as alignment references, eliminating the need for separate lithographic alignment steps and reducing both manufacturing complexity and cost while maintaining high positioning accuracy
Solution Approach 2:
The patent merges the formation of dielectric walls and gate plugs into a unified self-aligned process sequence. Both structures are created from the same material deposits and etching steps, combining multiple functions into a single integrated fabrication flow that reduces process complexity while ensuring precise relative positioning
Data Source
AI summary
Integrated circuit structures having a dielectric gate wall and a dielectric gate plug, and methods of fabricating integrated circuit structures having a dielectric gate wall and a dielectric gate plug, are described. For example, an integrated circuit structure includes a sub-fin having a portion protruding above a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is over the protruding portion of the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate wall is laterally spaced apart from the sub-fin and the plurality of horizontally stacked nanowires, the dielectric gate wall on the STI structure. A dielectric gate plug is on the dielectric gate wall.