Self-Aligned Diode Formation via Simultaneous Etching
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Solution Overview
Problem
Semiconductor diode fabrication faces challenges due to parasitic PN junctions and alignment inaccuracies in dopant diffusion processes, leading to unpredictable diode characteristics and compatibility issues with other process flows.
Innovation Solution
A method involving simultaneous etching of semiconductor and conductive layers to form self-aligned diode regions, using projecting regions as a hard mask for precise dopant implantation, which eliminates parasitic effects and improves alignment accuracy, allowing for the formation of well-defined PN junctions extending from the semiconductor surface to the insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dopant diffusion processes are used to fabricate diodes, then diodes can be formed in the semiconductor substrate, but masks used for dopant diffusion require strict alignment which is difficult to establish and results in defects due to variations in alignment accuracy
Solution Approach 1:
The method uses self-aligned etching where the diode region is defined by the intersection of the semiconductor layer and insulating layer patterns, eliminating the need for separate alignment-critical masking steps. The etching process automatically aligns the diode region with the underlying layers through the self-aligned nature of the process flow.
Solution Approach 2:
The insulating layer is formed with patterned regions before the semiconductor layer is deposited, pre-defining the areas where diodes will later be formed. This preliminary patterning establishes the geometric constraints that guide subsequent processing steps, ensuring proper alignment without requiring precise mask alignment during dopant diffusion.
2Ease of manufacture
If diodes are directly implanted in the semiconductor substrate, then diode fabrication is simplified, but parasitic PN junctions are formed which impact circuit behavior and reduce predictability
Solution Approach 1:
The method extracts the diode formation process from direct substrate implantation by forming diodes within a dedicated semiconductor layer that is deposited on top of the insulating layer. This separation removes the parasitic PN junctions that would form at the substrate interface, eliminating the harmful electrical effects while maintaining fabrication simplicity.
Solution Approach 2:
The insulating layer acts as an intermediary between the semiconductor substrate and the diode-forming semiconductor layer. This intermediate layer electrically isolates the diode structures from the substrate, preventing the formation of parasitic PN junctions while allowing the diodes to be formed using straightforward implantation processes.
3Manufacturing precision
If additional masking steps are used to improve alignment accuracy, then alignment precision improves, but process complexity and manufacturing cost increase
Solution Approach 1:
The self-aligned etching process uses the geometric patterns of the semiconductor and insulating layers to automatically define the diode region boundaries, eliminating the need for additional alignment-critical masking steps. The process flow is designed so that subsequent steps naturally align with previously formed structures through the self-aligned nature of the fabrication sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the predictability and performance of diodes by eliminating parasitic effects, improving alignment, and maintaining compatibility with other process flows like NVM technology, while reducing the need for additional masking steps and surface area usage.
Implementation Method 1
doping a semiconductor layer with a second conductivity type to form a sequence of PN junctions
Implementation Method 2
performing a first implantation of dopants having a second conductivity type into the semiconductor layer
Data Source
AI summary
In accordance with an embodiment of the present invention, a method of making a semiconductor device includes simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, where the semiconductor layer has a first conductivity type. The method further includes etching through first openings of a mask layer to form first implantation surfaces on the semiconductor layer and to form a plurality of projecting regions including conductive material of the conductive layer over the semiconductor layer. The method further includes using the plurality of projecting regions as a part of a first implantation mask, performing a first implantation of dopants having a second conductivity type into the semiconductor layer, to form a sequence of PN junctions forming diodes in the semiconductor layer. The diodes vertically extend from an upper surface of the semiconductor layer to the insulating layer.