Self-Aligned Double Patterning for Semiconductor Interconnects
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Solution Overview
Problem
As semiconductor device sizes decrease, traditional photolithographic and etching techniques become increasingly complex, limiting the formation of smaller, more efficient interconnects with fewer defects.
Innovation Solution
The implementation of a double-patterning lithography process using a stack of hard mask layers and a spacer layer to create precise patterns in a dielectric layer, allowing for the formation of smaller conductive lines and increased density of interconnects through a series of photolithography and etching steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithographic and etching techniques are used, then the formation of interconnects is straightforward, but the interconnect sizes cannot be reduced further and defect rates increase
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into two separate stages: first forming initial mandrels, then forming spacers around them to create the final interconnect pattern. This double-patterning approach segments the single complex lithography step into manageable stages, enabling smaller interconnect dimensions while controlling process complexity through systematic breakdown of the fabrication sequence.
2Area of stationary object
If device size is reduced, then device density increases, but the complexity of photolithographic and etching techniques increases
Solution Approach 1:
The patent employs dimensionality change by transitioning from planar 2D patterning to 3D structured fabrication. Mandrels are formed in a first layer, then spacers are deposited conformally around them, creating vertical sidewalls and multi-layer structures. This dimensional transition enables continued scaling of device area while managing process complexity through three-dimensional self-aligned patterning.
Solution Approach 2:
The patent applies preliminary action by first forming the mandrel structures before creating the final interconnect pattern. The mandrels serve as preliminary templates that define the spacing and positioning of subsequent spacer-formed interconnects. This preliminary patterning step establishes the geometric framework that guides the final high-precision pattern formation, enabling area reduction with controlled complexity.
3Manufacturing precision
If interconnect size is reduced, then device density improves, but defects increase
Solution Approach 1:
The patent applies self-service through self-aligned spacer formation where the spacers automatically position themselves relative to the mandrels without requiring additional alignment steps. The conformal deposition process ensures uniform spacer thickness and precise positioning, reducing alignment errors and manufacturing defects. This self-aligning mechanism enables reduced interconnect size while maintaining high reliability by eliminating manual alignment variability.
Solution Approach 2:
The patent uses mandrels as intermediary structures that facilitate the formation of final interconnects. These temporary mandrel structures serve as mediators between the lithography process and the final metal interconnect pattern. The spacers form around the mandrels, using them as reference features, and the mandrels are subsequently removed. This intermediary approach enables precise pattern transfer while reducing defects through self-aligned fabrication.
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. An embodiment comprises a target layer and masking layers over the target layer. First openings are formed in the uppermost layer of the masking layers. Spacers are formed along sidewalls of the first openings, remaining first openings having a first pattern. Second openings are formed in the uppermost layer of the masking layers, the second openings having a second pattern. The first pattern and the second pattern are partially transferred to the target layer.