Self-Aligned Double Patterning for Sub-50nm Logic Circuits
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Solution Overview
Problem
Conventional semiconductor device fabrication techniques face challenges in achieving smaller feature sizes and increasing feature density due to the limitations of photolithography, particularly with deep ultraviolet light, and struggle to create complex patterns like H-shaped and herringbone patterns without additional mask layers.
Innovation Solution
The method employs self-aligned double patterning using two lithographic operations to form two sets of parallel line features with a connection feature between them, without the need for an additional mask layer, by depositing and patterning a sacrificial material, followed by spacer material deposition and etching, which allows for the creation of H-shaped or herringbone patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography with deep ultraviolet light is used, then the manufacturing process is simple, but the minimum feature size is limited to approximately 50 nm
Solution Approach 1:
The patent divides the single lithography step into multiple sequential lithography steps, where each step patterns a portion of the final structure. This segmentation allows achieving sub-50nm features by combining multiple 193nm lithography steps with spacer formation, effectively bypassing the single-step resolution limit while maintaining process control
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional spacer-based patterning. By forming vertical spacer structures around patterned features and then performing anisotropic etching, the process creates additional dimensional control that enables sub-lithographic feature sizes through self-aligned double patterning
2Adaptability or versatility
If additional mask layers are added to create complex patterns like H-shaped and herringbone patterns, then the pattern complexity increases, but the device complexity and manufacturing steps increase
Solution Approach 1:
The patent employs self-aligned double patterning where the first lithography step and spacer formation automatically define the positions of subsequent features without requiring additional alignment steps. The spacers self-align to the patterned features, and the anisotropic etch selectively removes material based on the spacer geometry, enabling complex H-shaped and herringbone patterns to emerge from simple initial patterns without additional mask alignment complexity
Solution Approach 2:
The patent changes the etching parameters by using anisotropic etching with specific selectivity ratios (e.g., 5:1 or 10:1 selectivity between spacer material and underlying layers). This parameter control allows the etch to preserve spacer structures while removing sacrificial materials, enabling complex pattern formation through controlled material removal rather than additional deposition steps
3Productivity
If feature density is doubled through additional lithographic masks, then the feature density increases, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges the functions of multiple lithographic masks into a single mask by using the spacer structures as self-aligned pattern definition elements. The first lithography step patterns sacrificial features, and the subsequent spacer formation and anisotropic etch automatically create the second set of patterns without requiring a physical second mask, thereby doubling feature density while using only one lithographic mask
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively doubles the feature density and allows for the creation of complex logic circuit patterns using only two lithographic masks, enhancing the ability to fabricate smaller and more complex features in semiconductor devices.
Implementation Method 1
depositing a layer of a first material on a substrate and patterning the layer to form a first pattern
Implementation Method 2
depositing spacer material over the substrate and the first pattern
Implementation Method 3
etching the spacer material such that the spacer material is removed from the horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern
Data Source
AI summary
Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between the sets. In such embodiments, the sets of parallel line features along with the connection features are formed using two lithographic masks, without the need for an additional mask layer to form the connection. In other embodiments, other features in addition to the connection can be added in the same mask layer.