Self-Aligned Double Patterning for Microelectronic Devices
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Solution Overview
Problem
As memory cells become smaller and more closely spaced, it becomes increasingly difficult to manufacture smaller and more closely spaced memory cells due to limitations in current lithographic technologies and photoresist mask layers, which restrict the reduction of pitch in microelectronic devices.
Innovation Solution
A method involving the use of a first and second mask layer with patterned features, where the second mask layer is at least partially covered with a film, and openings are formed by removing the patterned feature of the second mask layer, allowing the pattern of a microelectronic layer to be defined through these openings, thereby reducing the pitch without requiring next-generation lithographic technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If current lithographic technologies and photoresist mask layers are used, then manufacturing process is simple, but pitch reduction is limited
Solution Approach 1:
The patterning process is divided into multiple stages: forming a first mask layer with initial features, depositing a second mask layer, selectively removing portions to create openings, and using these openings to define the final pattern. This segmentation allows pitch reduction beyond single-step lithographic capabilities while maintaining manufacturing feasibility
Solution Approach 2:
The first mask layer is formed with patterned features before the second mask layer is deposited. This preliminary patterning establishes a template that guides subsequent processing steps, enabling precise pitch control without requiring next-generation lithography tools
2Quantity of substance
If memory cells are made smaller and more closely spaced, then memory density increases, but manufacturing difficulty increases
Solution Approach 1:
The patent transitions from planar patterning to a multi-layer vertical structure. By stacking mask layers and using vertical openings through the second mask layer, the process achieves sub-lithographic pitch control in the horizontal dimension while utilizing the vertical dimension for process control, enabling higher memory cell density without proportionally increasing manufacturing difficulty
Data Source
AI summary
A method for transferring a pattern to one or more microelectronic layers. A first mask layer, having a patterned feature, and a second mask layer, having another patterned feature, are formed. The first mask layer and the second mask layer are at least partially covered with a film, and openings are formed in the film by removing the other patterned feature of the second mask layer. A pattern of a microelectronic layer is then defined by patterning the patterned feature of the first mask layer through the openings in the film. In one example, the patterned feature of the first mask layer is defined by forming spacers adjacent to the other patterned feature. In another example, the other patterned feature of the second mask layer is defined by removing a portion of the other patterned feature via an anisotropic etching process.