Self-Aligned Double Patterning for Semiconductor Fine Patterns
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Solution Overview
Problem
Existing double patterning techniques using self-aligned spacers for semiconductor device manufacturing face issues such as corner rounding and feature size variation across the wafer, making it challenging to fabricate fine patterns with feature sizes of 50 nm or below.
Innovation Solution
A method involving multiple mask layers and etching processes is employed, where a first mask pattern is formed, followed by a second mask pattern that partially covers the first, with selective etching to create trenches, and subsequent deposition and polishing of mask material layers to expose and remove intermediate patterns, allowing for precise etching of the device layer to form fine patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning technique utilizing self-aligned spacer is used, then feature size can be reduced to half the original lithographic pitch, but corner rounding and feature size variation occur
Solution Approach 1:
The patent segments the patterning process into multiple discrete steps: forming mandrels at a first pitch, depositing spacers, selectively removing mandrels, and repeating the process. This segmentation allows precise control over each stage, preventing corner rounding by avoiding the continuous exposure issues of single-step lithography and enabling independent optimization of each patterning cycle.
Solution Approach 2:
The patent performs preliminary actions by first forming mandrels with precise dimensions before adding spacers. The mandrels serve as pre-formed templates that define the initial pattern, and the spacers are subsequently deposited with controlled thickness to achieve the final half-pitch dimensions. This preliminary structuring prevents feature size variation by establishing a stable reference framework before the critical spacer formation step.
2Productivity
If feature sizes are reduced to 50 nm or below, then device density increases, but lithography system capabilities are exceeded
Solution Approach 1:
The patent divides the single high-resolution lithography step into multiple lower-resolution steps. Each lithographic exposure operates at a relaxed pitch (first pitch), but through sequential spacer formation and mandrel removal, the final feature size achieves half-pitch dimensions. This segmentation enables device density doubling without requiring the lithography system to resolve features at the final ultra-fine dimension in a single step.
Solution Approach 2:
The patent introduces spacers as intermediary structures that mediate between the lithographically-defined mandrels and the final target pattern. The spacers act as self-aligned hard masks that transfer the pattern from the mandrels to the underlying substrate, enabling precise feature definition at dimensions smaller than the lithography system's direct resolution capability.
3Manufacturing precision
If multiple mask layers and etching processes are used, then patterning precision improves, but process complexity increases
Solution Approach 1:
The patent merges multiple functions into the spacer structure: the spacers serve simultaneously as etch masks for removing mandrels, as self-aligned hard masks for defining final patterns, and as templates for subsequent material deposition. This functional consolidation reduces process complexity by eliminating the need for separate alignment and masking steps that would otherwise be required for each function.
Solution Approach 2:
The spacers are formed through self-aligned deposition processes where the spacer material automatically conforms to the mandrel sidewalls without requiring additional alignment steps. The spacers self-align to the mandrel positions, and the mandrels self-define the spacer locations, eliminating the need for complex photolithographic alignment between different mask layers and reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces corner rounding and feature size variation, enabling the fabrication of fine semiconductor device patterns with improved precision and consistency, extending the life of mainstream lithography systems.
Implementation Method 1
selectively etching the device layer not covered by the first and second mask patterns to thereby form a first trench therein
Implementation Method 2
depositing a mask material layer to fill the first trench and cover the intermediate mask pattern
Implementation Method 3
polishing the mask material layer to expose a top surface of the intermediate mask pattern
Data Source
AI summary
A method for making a semiconductor device includes forming a first mask pattern on a device layer, forming a second mask pattern on the first mask pattern, etching the device layer not covered by the first and second mask patterns to thereby form a first trench, trimming the first mask pattern to form an intermediate mask pattern, depositing a material layer to fill the first trench, polishing the material layer to expose a top surface of the intermediate mask pattern, removing the intermediate mask pattern to form an opening, etching the device layer through the opening to thereby form a second trench.