Self-Aligned Double Patterning for Semiconductor Feature Density
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Solution Overview
Problem
Conventional lithography technologies face challenges in projecting accurate images of increasingly smaller feature geometries due to wavelength limitations and growing feature density in integrated circuits, with self-aligned double patterning primarily used for dense line features rather than arbitrary patterns like logic circuits.
Innovation Solution
The method involves depositing a first material pattern on a substrate, followed by a spacer-etch process to create spacer material patterns, and then depositing and patterning a second material layer to form large features, enabling the creation of target layouts with doubled line feature density and inclusion of large features like connection and logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithography is used to pattern smaller features, then feature size decreases, but manufacturing precision deteriorates due to wavelength limitations
Solution Approach 1:
The patent divides the patterning process into multiple discrete steps: first forming initial patterns at relaxed dimensions, then using spacer deposition and etching to create additional patterns. This segmentation allows each step to operate within achievable precision limits while the cumulative result achieves the target density and dimension that would be impossible in a single lithography exposure.
Solution Approach 2:
The method performs preliminary patterning actions to create sacrificial patterns and spacers before final pattern formation. By pre-establishing these intermediate structures through deposition and selective etching, the process prepares the substrate in advance for the final pattern transfer, enabling achievement of target dimensions that exceed single-step lithography capabilities.
2Productivity
If feature density is increased to provide greater functionality, then circuit functionality improves, but manufacturing precision deteriorates due to resolution limits
Solution Approach 1:
The patent segments the high-density patterning into multiple fabrication steps: initial pattern formation, spacer material deposition, selective spacer etching, and pattern transfer. This multi-step segmentation enables achievement of doubled line density by creating patterns in stages, where each stage operates within the resolution capabilities of conventional lithography while the cumulative effect achieves the target high density.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional spacer structure formation and then back to two-dimensional pattern transfer. By utilizing the vertical dimension for spacer deposition and selective etching, the process creates additional pattern copies that double the effective line density without requiring proportional increases in lithographic resolution.
3Productivity
If self-aligned double patterning is used for dense line features, then line feature density doubles, but adaptability deteriorates for arbitrary patterns like logic circuits
Solution Approach 1:
The patent creates a universal patterning methodology that can handle both dense linear features and arbitrary logic circuit patterns through the same spacer-based mechanism. The process uses material property differences (spacer retention on vertical vs. horizontal surfaces) rather than geometry-specific rules, enabling application to diverse pattern types including contacts, gates, and interconnects with varying geometries.
Solution Approach 2:
The patent applies selective etching based on local surface geometry: spacers are removed from horizontal surfaces while retained on vertical surfaces. This local quality differentiation enables the same process to generate different pattern outcomes depending on the local feature geometry, providing versatility for various pattern types while maintaining the density-doubling mechanism.
4Length of moving object
If feature geometries are shrunk below minimum critical dimension, then feature size decreases, but manufacturing precision deteriorates beyond lithography capabilities
Solution Approach 1:
The patent segments the dimension-reduction process into indirect steps: first creating larger sacrificial patterns within lithography capabilities, then using spacer deposition thickness control and selective etching to generate the final sub-critical-dimension features. This segmentation bypasses the direct lithographic resolution limit by using spacer thickness (controllable by deposition parameters) rather than optical resolution to define the final feature dimensions.
Solution Approach 2:
The patent introduces spacer material as an intermediary between the lithographically-defined sacrificial pattern and the final target pattern. The spacer layer acts as a mediator that transfers and refines the pattern dimensions, enabling achievement of sub-critical-dimension features through controlled spacer deposition and selective removal rather than direct lithographic patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of semiconductor devices with narrower line features and larger features beyond the minimum critical dimension, effectively addressing the limitations of conventional lithography in achieving higher feature density and complexity in integrated circuits.
Implementation Method 1
a spacer-etch process that removes spacer material from horizontal surfaces of the substrate and the first pattern, yet leaves spacer material adjacent to vertical surfaces of the first pattern
Implementation Method 2
Passing light through transparent sections defined by the mask elements transfers the layout pattern for the layer onto the wafer. The projected light pattern interacts with a photosensitive coating on the wafer and, depending on the coating used, it is cured or rendered susceptible to removal in the areas that were exposed to the light
Data Source
AI summary
Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.