Self-Aligned Dual Stress Liners for CMOS Devices
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Solution Overview
Problem
Conventional CMOS fabrication techniques for dual stress liner (DSL) structures face challenges due to non-uniform thickness and misalignment issues, leading to defects and increased resistance in subsequent processing steps, particularly during BEOL processing.
Innovation Solution
A method for forming self-aligned, non-overlapping dual stress liner structures by conformally depositing stress liner layers and insulating layers, using photolithographic patterning and anisotropic etching to create a gapless interface between the layers, eliminating the need for a second lithographic patterning step and avoiding misalignment errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate lithographic patterning steps are used to form dual stress liner layers, then the stress liner structures can be formed with different patterns, but misalignment and non-uniform thickness occur leading to defects
Solution Approach 1:
The first stress liner layer serves as its own alignment reference for the second stress liner layer. By forming the second layer conformally over the patterned first layer and using the first layer's sidewalls as self-aligned masks, the process eliminates the need for separate lithographic alignment steps while maintaining precise pattern registration between layers.
Solution Approach 2:
The first stress liner layer is formed and patterned in advance to create self-aligned masks before forming the second stress liner layer. This preliminary patterning establishes precise alignment references that guide the subsequent conformal deposition and anisotropic etching steps, ensuring accurate pattern registration without requiring additional lithographic alignment.
2Reliability
If conventional dual stress liner structures are formed with overlapping layers, then coverage is ensured, but non-uniform thickness causes over-etching and damage to metal silicide regions
Solution Approach 1:
The dual stress liner structure is segmented into two distinct conformal layers rather than a single overlapping layer. The first stress liner layer is formed conformally and patterned to specific regions, then the second stress liner layer is formed conformally over the remaining areas. This segmentation eliminates overlapping regions and achieves uniform thickness while maintaining complete coverage through the self-aligned patterning approach.
3Manufacturing precision
If additional lithographic patterning steps are added to achieve precise alignment, then manufacturing precision improves, but process complexity and time increase
Solution Approach 1:
The first stress liner layer automatically serves as the alignment mask for the second stress liner layer through self-aligned anisotropic etching. This self-service mechanism eliminates the need for additional lithographic patterning steps, reducing process complexity while maintaining high alignment precision between the two stress liner layers.
4Manufacturing precision
If conformal deposition and self-aligned patterning are used, then alignment precision and thickness uniformity improve, but process steps increase
Solution Approach 1:
The formation of the second stress liner layer is merged with the patterning of the first layer through self-aligned conformal deposition and anisotropic etching. Instead of separate lithographic steps for each layer, the process combines the deposition and patterning operations where the first layer's pattern automatically defines the second layer's pattern, reducing the total number of process steps while achieving precise alignment and uniform thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a self-aligned, gapless interface between dual stress liner layers, reducing defects and ensuring uniform thickness, thereby enhancing the reliability and performance of CMOS devices by preventing over-etching and damage to metal silicide regions.
Implementation Method 1
the application of compressive stress to the conduction channel of a P-type transistor can improve the carrier (holes) mobility within the channel, while the application of tensile stress to the conduction channel of an N-type transistor can improve the carrier (electrons) mobility within the channel
Implementation Method 2
followed by a photolithographic patterning process to pattern the stress liner layer (140) and oxide layer (150)
Implementation Method 3
using photolithographic patterning and anisotropic etching to create a gapless interface between the layers
Data Source
AI summary
CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.