Self-Aligned Dual-Gate LDMOS Transistors for Reduced Gate Separation
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Solution Overview
Problem
Conventional dual-gate LDMOS transistors have large gate separation distances due to imperfect alignment, leading to increased transistor size, high resistance, and degraded dielectric isolation, which results in heating and reduced performance.
Innovation Solution
The development of self-aligned dual-gate LDMOS transistors where the vertical gate defines the lateral edge of the lateral gate, eliminating the need for separate gate alignment and allowing for minimized gate separation, thus reducing transistor size and maintaining robust dielectric isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional individual gate alignment is used, then gate alignment flexibility is maintained, but gate separation distance increases leading to larger transistor size and higher resistance
Solution Approach 1:
The vertical gate structure serves as its own alignment reference, defining the lateral edge of the lateral gate through self-alignment. This eliminates the need for separate alignment processes and achieves precise gate positioning without increasing gate separation distance, thereby reducing transistor size while maintaining alignment precision.
Solution Approach 2:
The patent combines the alignment functions of both gates into a single self-aligned process where the vertical gate defines the lateral gate position. This merging of alignment operations eliminates cumulative alignment errors and reduces the overall gate separation distance, resulting in smaller transistor footprints.
2Reliability
If larger gate separation distance is used to compensate for alignment errors, then alignment tolerance is improved, but resistance increases and performance degrades
Solution Approach 1:
The self-aligned vertical gate automatically defines the lateral gate edge with high precision, eliminating the need for large separation distances to compensate for alignment errors. This reduces the current path length and associated resistance while maintaining reliable alignment tolerance through the self-defining geometry.
3Ease of manufacture
If conventional processing is used, then manufacturing simplicity is maintained, but dielectric isolation between gates degrades
Solution Approach 1:
The vertical gate is formed first with its dielectric layers in place, creating a pre-established isolation structure. The lateral gate is then defined relative to this pre-formed vertical gate, ensuring that dielectric isolation is maintained between gates before subsequent processing steps occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in smaller transistor assemblies with shorter current paths, lower resistance, and improved heat management, enabling better performance and reliability.
Implementation Method 1
a vertical gate at least partially defines a lateral edge of a lateral gate, thereby eliminating the need to separately align each gate during transistor manufacturing
Implementation Method 2
A positive voltage VGS applied between gate electrode 116 and source electrode 104 creates negative charges in silicon semiconductor structure 102 under silicon dioxide layer 118, causing a minority-carrier channel to form
Implementation Method 3
creates negative charges in silicon semiconductor structure 102 under silicon dioxide layer 118
Implementation Method 4
When positive voltage VDS is applied across drain electrode 108 and source electrode 104, a p-n junction at the interface of n-well 124 and p-body 126 is reversed biased. Consequentially, essentially no current flows from drain electrode 108 to source electrode 104 by default
Implementation Method 5
The relative dopant concentration of drain n+ region 132 and n-well 124 causes a portion of n-well 124 referred to as a drift region 134 to carry the majority of voltage VDS, thereby enabling LDMOS transistor 100 to support a relatively large value of VDS without breakdown
Data Source
AI summary
A dual-gate, self-aligned lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure, a lateral gate including a first dielectric layer and a first conductive layer stacked on the silicon semiconductor structure in a thickness direction, and a vertical gate. The vertical gate includes a second dielectric layer and a second conductive layer disposed in a trench of the silicon semiconductor structure, the second dielectric layer defining an edge of the lateral gate in a lateral direction. A method for forming a dual-gate, self-aligned LDMOS transistor includes (a) forming a vertical gate of the LDMOS transistor in a trench of a silicon semiconductor structure and (b) defining a lateral edge of a lateral gate of the LDMOS transistor using the vertical gate.