Self-Aligned Dual-Gate Thin Film Transistor Manufacturing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing process for dual-gate thin film transistors, particularly planar dual-gate transistors, is complicated and non-self-aligned, leading to performance dispersion and large parasitic elements like parasitic capacitance, which is unacceptable for panel display applications.
Innovation Solution
A method for manufacturing self-aligned dual-gate thin film transistors by forming a bottom gate electrode and active region on a substrate, followed by coating a photoresist and using photolithography to etch the conductive thin film and form a top gate electrode, with the bottom gate electrode acting as a mask to ensure accurate alignment between the top and bottom gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional non-self-aligned manufacturing methods are used for dual-gate thin film transistors, then the manufacturing process is simpler, but the device has large performance dispersion and large parasitic capacitance
Solution Approach 1:
The bottom gate electrode serves as its own alignment reference for the top gate electrode formation. By using the bottom gate electrode structure itself as the mask reference during photolithography, the method achieves self-alignment without requiring additional alignment marks or complex multi-step alignment processes, thereby improving alignment precision while avoiding excessive process complexity
Solution Approach 2:
The bottom gate electrode is formed first and serves as a pre-established reference structure. The photolithography process is then designed to use this pre-formed bottom gate electrode as the alignment basis for forming the top gate electrode, ensuring that the alignment is determined in advance by the bottom gate structure rather than requiring complex real-time alignment
2Manufacturing precision
If non-transparent material is used for bottom gate electrode, then alignment is easier, but light transmission is blocked
Solution Approach 1:
The bottom gate electrode structure is designed with spatially varying properties: the region serving as alignment reference has different optical characteristics than the region serving as electrical gate. Specifically, the bottom gate electrode extends beyond the channel region to provide alignment reference marks that are visible during photolithography, while the region over the channel maintains appropriate electrical properties
Solution Approach 2:
The bottom gate electrode structure is segmented into functional regions: an extended reference region that protrudes beyond the channel to serve as alignment mark during photolithography, and a channel region that provides electrical gating function. This segmentation allows different portions to serve different purposes - alignment reference and electrical control - simultaneously
3Object-generated harmful factors
If self-aligned manufacturing method is implemented, then parasitic capacitance is reduced, but the manufacturing process becomes more complicated
Solution Approach 1:
The bottom gate electrode structure itself serves as the alignment reference for top gate formation, eliminating the need for separate alignment marks or additional reference structures. This self-service approach achieves self-alignment that reduces parasitic capacitance between gates while avoiding the complexity of adding extra alignment infrastructure to the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method achieves accurate alignment between the top and bottom gate electrodes, reducing parasitic elements such as parasitic capacitance and improving transistor performance by ensuring precise alignment and reducing performance dispersion.
Implementation Method 1
coating a photoresist on the conductive thin film and forming a photoresist pattern by exposure during which light is from a bottom of the substrate
Data Source
AI summary
Designs and fabrication of dual-gate thin film transistors are provided. An active region and a top gate electrode of the transistor can be made of a transparent thin film material. A photoresist can be coated onto a surface of the transparent conductive thin film for forming the top gate electrode. Light is from the bottom of the substrate during exposure. After the development, a photoresist pattern aligned with the bottom gate electrode is formed on the surface of the conductive thin film. The top gate electrode aligned with the bottom gate electrode is formed by etching the conductive thin film. The bottom gate electrode can be used as a mask, which may save the cost for manufacturing the transistor and improve the accuracy of alignment between the top gate electrode and the bottom gate electrode and the performance of the dual-gate thin film transistor.