Self-Aligned Emitter Wiring for Bipolar Transistor Resistance

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Solution Overview

Problem

In BiCMOS technology, achieving high ft frequency in bipolar transistors requires lower emitter and base resistances, which is challenging due to the smaller area between the base and emitter regions, especially for Silicon-Germanium heterojunction bipolar transistors (HBTs) operating at 300 GHz and higher frequencies.

Innovation Solution

A self-aligned sacrificial emitter process is used, involving etching to form an emitter opening between nitride spacers, depositing an in-situ doped emitter, performing a recess etch, and depositing tungsten wiring within emitter and base trenches via chemical mechanical polishing to reduce resistance and enhance current carrying capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the area between base and emitter regions is reduced to increase transistor speed, then the ft frequency is improved, but the emitter resistance increases

Engineering Contradiction:

Improvetransistor speedVSAvoidemitter resistance

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent introduces a vertical dimension by forming a via structure that extends downward from the emitter contact into the emitter region. This vertical connection path complements the horizontal contact, effectively reducing resistance without increasing the planar area between base and emitter regions, thus resolving the contradiction between speed and resistance.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The via structure is nested within the emitter contact structure, with the via extending into the emitter region beneath the contact. This nested configuration allows the via to provide an additional conductive path without occupying additional lateral space, enabling reduced resistance while maintaining compact area for high-speed operation.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Ease of manufacture

If conventional wiring structures are used, then the manufacturing process is simple, but the current carrying capability is insufficient for high frequency operation

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidcurrent carrying capability

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The emitter contact structure is segmented into multiple components: the surface emitter contact, the via structure extending into the emitter region, and the emitter trench. This segmentation creates multiple conductive pathways that collectively enhance current carrying capability while using standard semiconductor fabrication processes, maintaining manufacturing simplicity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The via structure is formed preliminarily during the emitter contact formation process, before final metallization layers are deposited. This preliminary action integrates the via formation into the existing manufacturing flow, avoiding additional complex process steps while ensuring the via is properly positioned and formed to enhance current carrying capability.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The self-aligned sacrificial emitter process results in lower emitter resistance and improved current carrying capabilities, leading to faster bipolar transistors with higher ft frequencies.

Implementation Method 1

performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

depositing an in-situ doped emitter into the emitter opening

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Implementation Method 3

performing a recess etch to partially remove a portion of the in-situ doped emitter

Methodology Applied

Scientific EffectEtching:

Implementation Method 4

planarizing the silicon dioxide layer via chemical mechanical polishing

Methodology Applied

Scientific EffectChemical mechanical polishing:

Implementation Method 5

etching an emitter trench over the recessed in-situ doped emitter

Methodology Applied

Scientific EffectEtching:

Implementation Method 6

depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS8841750B2Local wiring for a bipolar junction transistor including a self-aligned emitter region

Publication Date: 2014.09.23 GLOBALFOUNDRIES US INC

AI summary

Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.