Self-Aligned Field Plate for LDMOS Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing power MOSFET designs, such as LDMOS transistors, face challenges in reducing capacitance between the gate electrode and drain region, leading to increased resistance and power loss during switching, while also striving to increase device density without compromising reliability.
Innovation Solution
The approach involves forming a field plate over a field plate dielectric layer before forming the gate electrode, allowing for reduced spacing between the field plate and gate electrode, which is achieved by patterning the field plate and dielectric layer together using spacer structures, thereby reducing the width of the field plate dielectric layer and overall device area by 15 to 20%, enhancing device density without sacrificing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the field plate is spaced apart from the gate electrode to reduce capacitance, then power loss during switching is reduced, but the device area increases
Solution Approach 1:
The field plate dielectric layer is positioned in a vertical dimension between the gate electrode and drain region, allowing the field plate to be electrically coupled to the drain while maintaining physical separation from the gate electrode. This vertical stacking approach reduces the horizontal spacing requirements, thereby reducing device area while still achieving capacitance reduction through the dielectric layer.
2Area of stationary object
If the spacing between field plate and gate electrode is reduced to increase device density, then device area is reduced, but capacitance increases leading to higher power loss
Solution Approach 1:
A field plate dielectric layer is introduced as an intermediary between the field plate and the gate electrode. This dielectric layer allows the field plate to be positioned closer to the gate electrode (reducing device area) while simultaneously preventing direct electrical contact, thereby maintaining reduced capacitance and low power loss during switching.
3Manufacturing precision
If the field plate dielectric layer width is reduced to increase device density, then manufacturing precision is improved, but reliability may be compromised
Solution Approach 1:
The field plate dielectric layer is formed using a self-aligned process where the field plate itself serves as the alignment reference. The dielectric layer is deposited conformally over the field plate and then etched back, automatically aligning the dielectric layer width with the field plate width. This self-alignment eliminates the need for separate lithography alignment steps, improving manufacturing precision while maintaining reliability through consistent dimensional control.
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip that includes a gate dielectric, a gate electrode, a field plate dielectric layer, and a field plate. The gate dielectric layer is arranged over a substrate and between a source region and a drain region. The gate electrode is arranged over the gate dielectric layer. The field plate dielectric layer is arranged over the substrate and between the gate dielectric layer and the drain region. The field plate is arranged over the field plate dielectric layer and is spaced apart from the gate dielectric layer.