Self-Aligned Fin Bottom Electrodes for 4F2 Phase Change Memory
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Solution Overview
Problem
Manufacturing high-density memory devices with small dimensions and tight process variation specifications is challenging, particularly in achieving compatible integration with peripheral circuits and maintaining high-density layouts for large-scale memory devices using phase change based memory materials.
Innovation Solution
An array of memory cells on a semiconductor substrate is designed with word lines, doped regions, bottom electrodes, memory elements, top electrodes, and dielectric isolation structures, where the memory elements are formed using programmable resistive materials like chalcogenide alloys, and a method involving multiple lithographic and etching steps to create self-aligned structures that reduce cell size and align with peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If small pores and small quantities of programmable resistive material are used to reduce reset current, then reset current magnitude is reduced, but manufacturing precision requirements increase due to tight process variation specifications
Solution Approach 1:
The memory cell is segmented into distinct functional regions: access transistor, bottom electrode, phase change material, and top electrode. This segmentation allows independent optimization of each component's dimensions and materials, enabling precise control over reset current while maintaining manufacturing feasibility through standardized fabrication processes for each segment
Solution Approach 2:
Different regions of the memory cell are assigned different material properties and dimensions tailored to their specific functions. The bottom electrode uses materials with specific resistivity for current concentration, the phase change material has optimized thickness for phase transition, and the top electrode is designed for electrical contact. This local optimization achieves low reset current without requiring uniform high precision across the entire structure
2Quantity of substance
If very small dimensions are used to achieve high-density memory devices, then memory density is improved, but device complexity increases due to integration with peripheral circuits
Solution Approach 1:
The memory cell structure is designed to be compatible with standard CMOS peripheral circuits by using the same fabrication processes and material systems. The access transistor, bottom electrode, and interconnect structures can be integrated into existing CMOS process flows, allowing high-density memory arrays to be manufactured alongside peripheral logic without requiring separate specialized process lines
Solution Approach 2:
The memory cell utilizes vertical stacking of functional layers (bottom electrode, phase change material, top electrode) to achieve high density in the vertical dimension while maintaining planar compatibility with CMOS circuits. This three-dimensional arrangement of memory elements above the transistor plane enables increased storage density without increasing the lateral footprint that would complicate circuit integration
3Ease of manufacture
If conventional memory cell structures are used to maintain ease of manufacture, then manufacturing simplicity is preserved, but cell size reduction is limited
Solution Approach 1:
The phase change material layer is deposited to a predetermined thickness and composition before subsequent electrode formation steps. This preliminary preparation of the active material layer with optimized properties enables the subsequent electrode patterning and formation to proceed using standard lithographic and deposition processes, achieving small cell dimensions without requiring complex or non-standard manufacturing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the production of high-density memory devices with reduced cell size and improved process variation tolerance, supporting large-scale manufacturing while maintaining compatibility with peripheral circuits, thus enhancing the density and reliability of memory arrays.
Implementation Method 1
Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase.
Implementation Method 2
The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or break down the crystalline structure
Data Source
AI summary
Arrays of memory cells are described along with devices thereof and method for manufacturing. Memory cells described herein include memory elements comprising programmable resistive material and self-aligned bottom electrodes. In preferred embodiments the area of the memory cell is 4F2, F being the feature size for a lithographic process used to manufacture the memory cell, and more preferably F being equal to a minimum feature size. Arrays of memory cells described herein include memory cells arranged in a cross point array, the array having a plurality of word lines and source lines arranged in parallel in a first direction and having a plurality of bit lines arranged in parallel in a second direction perpendicular to the first direction.