Self-Aligned Fin-Cut Isolation for Dense Nanowire Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node is exacerbated by the constraints on lithographic processes used to pattern semiconductor features, leading to a trade-off between critical dimension and spacing, particularly in multi-gate and nanowire transistors.
Innovation Solution
A fin cut isolation approach is implemented after gate patterning, allowing for self-aligned isolation of non-planar transistors, reducing the need for multiple dummy gates and enabling higher transistor densities by aligning fin isolation dimensions perfectly with gate electrodes, thus maintaining strain and optimizing space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern semiconductor features at small dimensions, then critical dimension control becomes difficult, but feature spacing must be increased
Solution Approach 1:
The patent introduces a vertical dimension by forming fins that extend upward from the substrate, transforming a 2D planar transistor into a 3D structure. This allows the channel length to be effectively increased in the vertical direction while maintaining small lateral dimensions, thereby improving critical dimension control without increasing feature spacing in the planar direction.
Solution Approach 2:
The patent segments the gate structure into multiple fins, where each fin acts as an independent vertical channel. This segmentation allows each fin to be precisely controlled during lithography while the collective array of fins provides the necessary current drive, resolving the contradiction between small critical dimensions and adequate feature spacing.
2Productivity
If device dimensions are scaled down to increase transistor density, then short channel control deteriorates, but mobility improvement is lost
Solution Approach 1:
By extending the channel into the vertical dimension through fin formation, the patent achieves effective channel length extension without increasing lateral device footprint. This maintains high transistor density while improving short channel control through the additional vertical confinement, and the fin structure enhances carrier mobility through strain engineering.
Solution Approach 2:
The patent implements a nested structure where multiple nanowires or fins are stacked vertically within a compact lateral footprint. This nesting approach allows high transistor density by packing multiple channels in the vertical direction while each nested element maintains proper channel length for short channel control and can be strained for mobility improvement.
3Reliability
If multiple dummy gates are used to maintain isolation, then space utilization decreases, but fin isolation alignment becomes complex
Solution Approach 1:
The patent employs self-aligned fin isolation where the isolation structures are automatically positioned relative to the fins through the fin formation process itself, eliminating the need for separate dummy gates. The fins serve their own isolation function by defining the active regions, thereby improving space utilization while maintaining reliable fin isolation.
Solution Approach 2:
The patent removes the need for dummy gates by integrating isolation functionality directly into the fin structure formation. The extraneous dummy gate elements are taken out of the design, and isolation is achieved through the essential fin structures themselves, improving space utilization while maintaining isolation reliability.
Data Source
AI summary
Fin cuts in neighboring gate and source or drain regions for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a horizontal stack of semiconductor nanowire portions. A dielectric gate spacer is vertically over the horizontal stack of semiconductor nanowire portions. A gate isolation structure is laterally adjacent to a first side of the horizontal stack of semiconductor nanowire portions. A source or drain isolation structure is laterally adjacent to a second side of the horizontal stack of semiconductor nanowire portions.