Self-aligned floating gate in vertical memory structure
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Solution Overview
Problem
In three-dimensional floating-gate flash memory technologies, achieving self-aligned floating gates is challenging, which affects the reliability and tunneling current between the control gate and the channel, leading to inefficiencies in memory cell performance.
Innovation Solution
The implementation of a method where the floating gate is formed with a thickness equal to or greater than the control gate, using sacrificial layers and blocking dielectric films to ensure self-alignment, reducing the tunneling current and enhancing memory cell reliability by maintaining the shortest path through the floating gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional floating gate formation methods are used in three-dimensional flash memory, then the manufacturing process is simpler, but the alignment between control gate and floating gate is poor, leading to increased tunneling current and reduced reliability
Solution Approach 1:
The patent applies preliminary action by forming sacrificial layers and blocking dielectric films before forming the floating gate. The sacrificial layers are deposited and patterned first, then blocking dielectric films are formed over them, and finally the floating gate is formed. This sequence ensures that the floating gate is pre-positioned relative to the control gate, achieving self-alignment and reducing tunneling current before the actual memory cell operation begins.
Solution Approach 2:
The patent uses sacrificial layers and blocking dielectric films as intermediary structures to achieve proper floating gate alignment. These intermediary layers are deposited, patterned, and etched back to create precise positioning features that guide the floating gate formation. The blocking dielectric films act as mediators that define the exact location where the floating gate should be formed, ensuring self-alignment with the control gate.
2Loss of energy
If the floating gate thickness is reduced to minimize tunneling current, then tunneling current decreases, but the manufacturing precision required to maintain self-alignment increases
Solution Approach 1:
The patent implements self-service through self-aligned fabrication processes where the floating gate automatically positions itself relative to the control gate using the sacrificial layers and blocking dielectric films as references. The etch back process removes excess material while preserving the aligned structure, and the floating gate formation follows the contours created by the sacrificial layers, ensuring automatic alignment without requiring additional alignment steps or higher manufacturing precision.
Solution Approach 2:
The patent changes the thickness parameter of the floating gate to be equal to or greater than the control gate thickness, which is different from conventional designs. This parameter change, combined with the self-aligned formation process, ensures that the floating gate maintains proper positioning while having sufficient thickness to minimize tunneling current. The blocking dielectric film thickness is also controlled to be no thicker than the sacrificial layers to maintain proper alignment.
3Manufacturing precision
If sacrificial layers and blocking dielectric films are used to achieve self-alignment, then alignment precision improves, but the number of fabrication steps increases
Solution Approach 1:
The patent merges multiple functions into the sacrificial layers and blocking dielectric films. These structures serve as both alignment references for floating gate formation and as part of the final memory cell structure. The blocking dielectric films become the insulating layer between the control gate and floating gate, and the sacrificial layers define the floating gate pattern. This merging reduces the need for separate alignment structures and integrates the alignment function into the functional components themselves.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced tunneling current and increased reliability of the floating gate flash memory cells by ensuring the control gate and floating gate are self-aligned, improving the overall performance of the memory cells.
Implementation Method 1
a tunneling dielectric film separating the floating gate from the memory cell body
Data Source
AI summary
Methods for building a memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate.