Self-Aligned Blocking Structure for Scaled FinFET Gate Contacts
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity of processing and manufacturing due to the scaling-down of feature sizes, which complicates the fabrication process.
Innovation Solution
The method involves self-aligned formation of blocking structures in the gate and contact structures, using photolithography and self-aligned processes to pattern fins, and employing multi-patterning techniques to create smaller pitches, along with the use of high-k dielectric layers and metal gate electrodes to form semiconductor device structures like FinFETs and gate-all-around devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but processing complexity increases and manufacturing reliability deteriorates
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including forming first and second blocking structures at different levels, selective etching steps, and staged material deposition. This segmentation allows complex 3D structures to be built through manageable sequential steps, reducing processing complexity while enabling continued scaling for improved productivity
Solution Approach 2:
The patent transitions from 2D planar structures to 3D vertical structures by forming blocking structures that extend through multiple layers and levels. This dimensional transition enables increased functional density without proportionally increasing processing complexity, as the vertical stacking leverages the third dimension to pack more functionality into the same footprint
2Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but manufacturing reliability deteriorates
Solution Approach 1:
Blocking structures are formed in advance to define and protect critical regions before subsequent processing steps. These pre-formed blocking structures act as protective elements that prevent defects from propagating through later fabrication steps, cushioning against manufacturing variability and maintaining reliability as features scale down
Solution Approach 2:
The blocking structures are formed using self-aligned processes where previously deposited materials serve as alignment references for subsequent layers. This self-service approach eliminates the need for additional alignment steps and external referencing, reducing the accumulation of alignment errors that would otherwise degrade manufacturing reliability at smaller feature sizes
3Manufacturing precision
If self-aligned processes are used to form blocking structures, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
Blocking structures are formed as preliminary features that establish the geometric framework for subsequent components. By pre-defining critical dimensions and positions through these blocking structures, the patent achieves high manufacturing precision in later steps without requiring equally complex alignment processes, as the preliminary structures serve as built-in references
Solution Approach 2:
The blocking structures act as intermediary elements that mediate between different fabrication stages. These intermediate structures translate design specifications into physical form factors that guide subsequent processing, enabling high precision manufacturing while managing overall device complexity by breaking down the fabrication sequence into manageable intermediary steps
Data Source
AI summary
A method for forming a semiconductor device structure includes forming a fin structure over a substrate. The method also includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes forming source/drain epitaxial structures over opposite sides of the gate structure. The method also includes forming an inter-layer dielectric structure over the source/drain epitaxial structures. The method also includes removing a portion of the gate structure and the ILD structure to form an opening. The method also includes forming a blocking structure in the opening.