Self-Aligned Gate Insulating Feature to Prevent Contact Bridging
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Solution Overview
Problem
As transistors in advanced technology nodes experience dimensional shrinkage, the distance between gate electrodes and contact features becomes smaller, leading to insufficient protection by existing gate spacers and contact etching stop layers, resulting in potential bridging issues during the formation of contact features.
Innovation Solution
A semiconductor structure with a self-aligned insulating feature is developed, comprising a cap portion made of a dielectric material with a higher dielectric constant than the gate spacers, extending beyond the edge of the gate electrode, and a barrier layer to prevent diffusion, which is formed using a method involving multiple dielectric layers and etching processes to ensure adequate protection and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between gate electrode and contact feature is reduced to increase transistor integration density, then the number of transistors per unit area increases, but bridging defects occur during contact feature formation
Solution Approach 1:
The patent applies preliminary action by forming the insulating feature (comprising gate spacer and contact etching stop layer) before contact hole etching. The gate spacer is deposited and patterned first, followed by the contact etching stop layer, ensuring protective structures are in place before contact features are formed. This sequence prevents bridging defects by having protection structures ready in advance.
Solution Approach 2:
The patent introduces an intermediary structure (contact etching stop layer) between the gate spacer and the contact hole etching process. This intermediate layer with higher etch selectivity acts as a mediator that protects the gate electrode during contact hole formation, enabling precise patterning without bridging while maintaining the reduced distance for high integration density.
2Reliability
If gate spacer thickness is increased to prevent bridging defects, then bridging protection improves, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by using two different materials with different properties: the gate spacer provides mechanical protection and alignment, while the contact etching stop layer with higher dielectric constant provides etch protection and has lower parasitic capacitance due to its thinner required thickness. This localized differentiation of material properties solves both protection and capacitance issues.
Solution Approach 2:
The patent uses a composite structure consisting of gate spacer material (e.g., silicon nitride) and contact etching stop layer material (e.g., silicon oxynitride or silicon oxide). This composite approach combines the protective functions of both materials, where the gate spacer provides structural support and the contact etching stop layer provides selective etch protection, achieving bridging prevention with optimized capacitance characteristics.
3Reliability
If contact etching stop layer with higher dielectric constant is used, then etch selectivity and protection improve, but manufacturing process complexity increases
Solution Approach 1:
The patent applies parameter changes by selecting materials with specific dielectric constant values and etch selectivity ratios. The contact etching stop layer uses materials like silicon oxynitride or silicon oxide that have higher dielectric constants and appropriate etch selectivity relative to the gate spacer material. These parameter optimizations enable effective protection while using standard semiconductor manufacturing processes.
Solution Approach 2:
The patent segments the protective structure into two distinct functional layers: the gate spacer for structural support and alignment, and the contact etching stop layer for etch protection. This segmentation allows each layer to be optimized for its specific function and enables independent process control, reducing overall manufacturing complexity despite the additional layer.
Data Source
AI summary
A semiconductor structure includes a substrate, a channel structure, a gate structure, two gate spacers and an insulating feature. The gate structure is disposed on the channel structure, and includes an upper gate portion which is located at a level higher than that of an uppermost surface of the channel structure. The two gate spacers are respectively located at two opposite sides of the upper gate portion, and each of the gate spacers has an upward surface having a concave profile. The insulating feature is disposed over the upper gate portion and against the concave profiles of the gate spacers to have an inverted U-shaped profile. The insulating feature includes a cap portion which is disposed on an upper surface of the upper gate portion and extends beyond an edge of the upper surface of the upper gate portion. Methods for manufacturing the semiconductor structure are also disclosed.