Self-Aligned Gate Contact Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The existing semiconductor structure formed by the self-aligned contact process requires improved performance, particularly in reducing parasitic capacitance and enhancing electrical connection between gate and source-drain structures, while maintaining high component density and integration.
Innovation Solution
A semiconductor structure and fabrication method involving a substrate with multiple gate structures, source-drain doped layers, and conductive structures, where a conductive layer is formed to connect the gate and source-drain doped layers, and a second dielectric layer is used to reduce short-circuits and increase spacing, thereby improving electrical performance and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a self-aligned contact process is used to fabricate a conductive structure on the surfaces of source and drain regions, then the flash memory size can be reduced, but the electrical performance and parasitic capacitance need to be improved
Solution Approach 1:
The conductive structure is divided into multiple segments: source-drain doped layers, conductive structures in the first dielectric layer, and a coplanar conductive layer. This segmentation allows for optimized electrical connections while maintaining compact dimensions, resolving the contradiction between small size and electrical performance.
Solution Approach 2:
The conductive layer is formed coplanar with the top surface of the first dielectric layer, extending in the lateral dimension rather than only vertically. This dimensional approach increases spacing and reduces parasitic capacitance without increasing the vertical profile, thus improving electrical performance while maintaining compact size.
2Productivity
If component density and integration degree are increased, then higher performance is achieved, but parasitic capacitance and short-circuits increase
Solution Approach 1:
The first dielectric layer serves as an intermediary between the source-drain doped layers and the conductive layer. It provides electrical isolation and spacing, reducing parasitic capacitance between adjacent conductive elements while allowing high component density through the self-aligned contact structure.
3Reliability
If spacing between conductive elements is increased to reduce parasitic capacitance, then electrical performance improves, but device area increases
Solution Approach 1:
The dielectric layer provides localized spacing and isolation exactly where needed between conductive elements, rather than requiring uniform spacing throughout the entire device. This allows compact overall device area while maintaining adequate spacing to reduce parasitic capacitance in critical regions.
Data Source
AI summary
A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate, and a first dielectric layer, a first gate structure and a plurality of second gate structures over the substrate. A second protection layer is formed on a top of a second gate structure. A first source-drain doped layer is formed between the first gate structure and an adjacent second gate structure. The first dielectric layer covers sidewalls of the first and second gate structures, and exposes a top surface of the second protection layer. The semiconductor structure also includes a first conductive structure in the first dielectric layer over the first source-drain doped layer, and a conductive layer on the first gate structure and the first conductive structure. A top surface of the conductive layer is coplanar with a top surface of the first dielectric layer.