Self-aligned gate contact formation with cross-coupling
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Solution Overview
Problem
Existing methods for forming self-aligned gate contacts and cross-coupling contacts in field-effect transistors often result in weak contacts due to over-thinning of the conductor and damage to semiconductor material during the etching process, particularly when planarizing the conductor and removing gate caps.
Innovation Solution
The method involves forming epitaxial semiconductor layers adjacent to sidewall spacers, recessing these spacers and gate structures using selective etching processes, and forming cross-coupling contacts that connect the gate structures with the epitaxial layers, ensuring protection and increased thickness of the contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate cap is removed by etching to open the top surface of the metal gate for cross-coupling contact formation, then the cross-coupling contact can connect the gate with source/drain regions, but the semiconductor material forming the source or drain region is exposed to the etching process which damages the semiconductor material
Solution Approach 1:
A sacrificial oxide layer is formed over the gate structure before etching the gate cap. This oxide layer acts as an intermediary protective barrier that shields the underlying semiconductor material from etching damage while allowing the gate cap to be removed for cross-coupling contact formation. The oxide is selectively removed later without damaging the semiconductor.
2Manufacturing precision
If the conductor deposited to form the self-aligned cross-coupling contact is planarized, then the surface is flattened for subsequent processing, but the conductor becomes overly thin which weakens the cross-coupling contact
Solution Approach 1:
The gate structure is recessed before depositing the conductor for the cross-coupling contact. This preliminary action creates additional vertical space that compensates for the conductor thinning that occurs during subsequent planarization. The conductor maintains adequate thickness and strength even after CMP processing.
3Ease of manufacture
If self-aligned contacts are formed using conventional methods with patterned resist constraints, then the process is simpler, but the alignment precision and contact accuracy are reduced compared to sidewall spacer-constrained etching
Solution Approach 1:
Sidewall spacers are formed on the gate structure that automatically define the contact opening positions through self-alignment. The spacers serve as their own alignment reference, eliminating the need for separate alignment steps and ensuring high precision contact placement while maintaining process efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the strength and reliability of self-aligned gate and cross-coupling contacts by maintaining the integrity of the semiconductor material and increasing the thickness of the cross-coupling contacts, reducing the risk of thinning and damage during planarization.
Implementation Method 1
forming an epitaxial semiconductor layer adjacent to the sidewall spacer
Implementation Method 2
the sidewall spacer is recessed with a first etching process. After recessing the spacer, the gate structure is recessed with a second etching process
Data Source
AI summary
Methods of forming self-aligned gate contacts and cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include self-aligned gate contacts and cross-coupling contacts. A sidewall spacer is formed at a sidewall of a gate structure and an epitaxial semiconductor layer is formed adjacent to the sidewall spacer. After forming the epitaxial semiconductor layer, the sidewall spacer is recessed with a first etching process. After recessing the spacer, the gate structure is recessed with a second etching process. After recessing the gate structure, a cross-coupling contact is formed that connects the gate structure with the epitaxial semiconductor layer.