Self-Aligned Gate Contact Structure for Overlay and Leakage Control
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Solution Overview
Problem
The aggressive scaling down of semiconductor IC dimensions leads to densely spaced gate structures and source/drain contacts, posing challenges in forming gate contacts and source/drain contact vias due to high overlay precision demands, which existing techniques have not adequately addressed, resulting in issues like electrical shorts, leakage, and increased parasitic capacitance.
Innovation Solution
The method involves depositing a liner over the gate structure and gate spacers with different etching selectivity than the self-aligned contact dielectric feature to prevent damage during the formation of gate contact openings, thereby reducing parasitic capacitance, electrical shorts, or leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If aggressive scaling down of IC dimensions is performed, then production efficiency improves and costs decrease, but overlay precision demands increase leading to electrical shorts and leakage
Solution Approach 1:
The gate spacer serves a dual function: as a structural element defining the gate contact opening location, and as a self-aligned mask protecting the gate structure during etching. This self-service approach eliminates the need for separate alignment processes, achieving high precision without additional manufacturing steps.
Solution Approach 2:
The gate spacer is formed in advance before gate contact opening formation. This preliminary action establishes the precise location and protects the gate structure during subsequent etching, ensuring high overlay precision is achieved without requiring complex real-time alignment procedures.
2Adaptability or versatility
If gate contacts are formed in densely spaced structures, then device functionality is achieved, but parasitic capacitance increases and electrical shorts occur
Solution Approach 1:
The gate spacer acts as an intermediary structure between the gate electrode and the gate contact opening. It provides precise spatial definition and electrical isolation, enabling dense packing while controlling parasitic capacitance through its controlled thickness and material properties.
Solution Approach 2:
The gate spacer provides localized protection and definition exactly where needed - at the gate contact opening location. Its presence is concentrated only in critical areas, allowing dense overall structure while maintaining local precision to prevent shorts and control parasitic effects.
3Ease of manufacture
If conventional etching is used for gate contact openings, then manufacturing simplicity is maintained, but gate spacer damage occurs causing leakage and shorts
Solution Approach 1:
The etching process parameters are changed to be selective - the etchant is formulated to etch the dielectric material at a different rate than the gate spacer material. This parameter change allows conventional etching equipment to be used while achieving differential etching that protects the gate spacer from damage.
Solution Approach 2:
The potential harm of aggressive etching that could damage the gate spacer is converted into a benefit through selective etching. The same etching process that removes dielectric material to create the opening automatically protects the gate spacer due to material selectivity, turning a potential defect into a protective mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and electrical shorts by protecting gate spacers and allowing for precise formation of gate contacts, enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
The material of the liner is selected to have different etching selectivity from the self-aligned contact dielectric feature such that the liner prevents or reduces damages to the gate spacers when forming a gate contact opening
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.