Self-Aligned Gate Contact Structure for Overlay Error Tolerance
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Solution Overview
Problem
Conventional semiconductor fabrication techniques face challenges in precise alignment of contacts, leading to misalignment issues such as increased parasitic capacitance and potential shorts between source/drain and gate structures, particularly in self-aligned contact configurations.
Innovation Solution
A self-aligned contact structure is developed using a self-assembly monolayer (SAM) to precisely align a 'hat' structure over the multi-layer metal gate, which shields the gate during etching and eliminates the need for a hard mask, allowing for self-aligned source/drain contacts that reduce parasitic capacitance and prevent shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional contact alignment techniques are used, then manufacturing process is simpler, but alignment precision deteriorates leading to misalignment and increased parasitic capacitance
Solution Approach 1:
The gate structure itself serves as the alignment reference for the contact holes. The contact holes are formed to be self-aligned with the gate structure, eliminating the need for separate alignment processes. This self-service approach achieves high alignment precision while simplifying the overall fabrication process by removing complex alignment steps.
Solution Approach 2:
The gate structure is formed first as a preliminary step, establishing the alignment reference before contact hole formation. This preliminary action of creating the gate structure with its specific geometry enables subsequent self-aligned contact formation, ensuring precise alignment without requiring complex overlay processes.
2Manufacturing precision
If self-aligned contact structures are used, then alignment precision improves, but parasitic capacitance increases due to closer contact with gate metal
Solution Approach 1:
The contact holes are positioned in a different spatial dimension relative to the gate structure. By forming contact holes that extend vertically through the dielectric layer and aligning them with the gate structure's lateral dimensions, the design achieves precise alignment while maintaining adequate vertical spacing. This dimensional approach allows the contact to be self-aligned without being laterally close to the gate metal, thereby reducing parasitic capacitance.
Solution Approach 2:
The dielectric layer acts as an intermediary between the contact holes and the gate metal. This intermediate layer provides electrical isolation and reduces parasitic capacitance while allowing the contact holes to be self-aligned with the gate structure. The intermediary enables both precise alignment and electrical isolation to coexist.
3Ease of manufacture
If etching is performed to create contact holes, then contact formation is enabled, but dishing and horn formation occur causing insufficient isolation and potential shorts
Solution Approach 1:
The etching parameters are optimized to control the etching profile and minimize dishing and horn formation. By adjusting etching conditions such as gas flow rates, pressure, and power, the process achieves uniform etching depth and profile without excessive material removal at the edges. This parameter control prevents horn formation that could lead to shorts while maintaining adequate isolation.
Solution Approach 2:
The etching process incorporates feedback control to monitor and adjust etching parameters in real-time. This feedback mechanism detects variations in etching rate and profile, allowing dynamic adjustment to prevent dishing and horn formation. The feedback ensures consistent etching quality and maintains reliable isolation throughout the contact hole formation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures precise alignment and reduced parasitic capacitance between source/drain and gate structures, enhancing the reliability and consistency of field effect transistor (FET) performance by avoiding overlay errors and etching-related damages.
Implementation Method 1
During fabrication, a self-assembly monolayer (SAM) is used to precisely align the hat over the multi-layer metal gate
Data Source
AI summary
A self-aligned contact (SAC) and method for making the same is disclosed. In an aspect a field effect transistor (FET) structure comprises a channel connecting a first source or drain (S/D) region to a second S/D region, a gate structure, comprising a multi-layer metal gate between gate spacers, disposed above a gate region that at least partially surrounds the channel, a self-alignment structure, also referred to as a “hat”, disposed above the gate structure and covering at least the multi-layer metal gate and the gate spacers, and a first S/D contact that is self-aligned to the hat and connected to the first S/D region. During fabrication, a self-assembly monolayer (SAM) is used to precisely align the hat over the multi-layer metal gate. The S/D contacts are then self-aligned to the hat, even if the etch mask has an overlay error. The hat also shields the gate structure during an etch.