Self-Aligned Common Gate Contact for Stacked Transistors

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Solution Overview

Problem

Current stacked transistor designs face challenges in fabricating a common self-aligned gate contact, leading to higher resistance and misalignment issues due to separate wiring and complex process steps.

Innovation Solution

A semiconductor structure with a top transistor stacked above a bottom transistor, featuring a single self-aligned gate contact that is electrically connected to both the top and bottom gate conductors, using a self-aligned process and shared conductive materials for the gate contact and top gate conductor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If separate gate contacts are used for top and bottom transistors, then alignment can be achieved through separate fabrication processes, but resistance increases and device complexity increases

Engineering Contradiction:
Improvealignment precisionVSAvoidelectrical resistance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent merges the gate contacts of the top and bottom transistors into a single common gate contact structure. This single contact is formed through a self-aligned process that simultaneously contacts both gate conductors, eliminating the need for separate contacts. The merging reduces the number of interfaces and contact resistance points while improving alignment precision through the self-aligned fabrication approach.

Inventive Principle:
Principle #5Merging (Combining)

2Ease of manufacture

If separate gate contacts are used for top and bottom transistors, then each contact can be independently fabricated, but device complexity and fabrication complexity increase

Engineering Contradiction:
Improveindependent fabrication capabilityVSAvoidfabrication process complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent combines the fabrication of two separate gate contacts into a single self-aligned contact formation process. The self-aligned process allows the single contact to be precisely positioned relative to both gate conductors without requiring separate alignment steps, thereby reducing fabrication process complexity while maintaining ease of manufacture.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The self-aligned contact structure is formed in advance during the gate conductor formation process itself, rather than as a subsequent separate step. This preliminary action integrates the contact formation into the existing fabrication flow, reducing overall process complexity while maintaining manufacturing ease.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If a single common gate contact is used, then resistance is reduced and alignment is improved, but fabrication complexity increases

Engineering Contradiction:
Improveelectrical resistanceVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate contact structure is self-aligned, meaning it automatically positions itself relative to the gate conductors during fabrication without requiring external alignment steps. The self-aligned process uses the gate conductor structure itself as the reference for contact positioning, eliminating the need for complex alignment procedures and reducing fabrication complexity while maintaining low resistance and precise alignment.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20230420503A1Common self aligned gate contact for stacked transistor structures
Publication Date: 2023.12.28 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20230420503A1 patent drawing
  • US20230420503A1 patent drawing
  • US20230420503A1 patent drawing

AI summary

A stacked semiconductor structure including a top transistor stacked above a bottom transistor, and a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.