Self-Aligned Gate Contact Formation in Vertical Field Effect Transistors
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Solution Overview
Problem
As integrated circuit designs aim for increased device density, forming vertical field effect transistors (VFETs) with reduced fin and gate pitches is challenging due to the risk of defects like shorts, and existing methods require additional gate extensions that consume chip area, negating scaling benefits.
Innovation Solution
The method involves forming self-aligned gate and source/drain contacts in VFETs by using isolation regions and spacer layers, eliminating the need for gate extensions and minimizing the risk of shorts, thereby enabling increased device density without performance impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate extension is formed to provide landing surface for gate contact, then gate contact can be formed, but additional chip area is consumed, canceling out scaling benefits
Solution Approach 1:
The gate contact is formed by etching laterally through the dielectric layer to reach the gate sidewall, rather than forming a vertical contact through the gate extension. This lateral approach in the horizontal dimension eliminates the need for vertical gate extension structures, thereby saving chip area while still achieving proper gate contact formation.
Solution Approach 2:
The gate extension structure is completely removed from the design. Instead of adding a gate extension to provide a landing surface, the invention extracts this unnecessary component and directly forms the gate contact to the original gate structure through lateral etching, eliminating the area consumption associated with gate extensions.
2Quantity of substance
If fin pitch is reduced to increase device density, then device density increases, but risk of shorts between gate contact and source/drain regions increases
Solution Approach 1:
The gate contact opening is formed to expose the gate sidewall before any source/drain contact formation occurs. By establishing the gate contact position and depth in advance, with the bottom of the opening positioned above the spacer layer, the design preemptively prevents potential shorts between gate and source/drain contacts that could occur with reduced fin pitch.
Solution Approach 2:
The dielectric layer acts as an intermediary barrier between the gate contact and the source/drain regions. By controlling the depth of the gate contact opening to terminate above the spacer layer, the dielectric material provides electrical isolation that prevents shorts while still allowing proper gate contact formation in high-density configurations.
3Length of moving object
If self-aligned gate is formed to reduce gate pitch, then gate pitch is reduced, but gate contact formation becomes problematic
Solution Approach 1:
The gate sidewall itself serves as the landing surface for the gate contact. By etching laterally to expose the gate sidewall, the structure uses its own geometry to provide the contact interface, eliminating the need for separate gate extension structures. This self-aligned approach simplifies manufacturing while maintaining reduced gate pitch.
Data Source
AI summary
Disclosed are methods wherein vertical field effect transistor(s) (VFET(s)) and isolation region(s) are formed on a substrate. Each VFET includes a fin extending vertically between source/drain regions, a spacer layer and a gate around the fin, and a source/drain sidewall spacer around an upper source/drain region. Optionally, a gate sidewall spacer is adjacent to the gate at a first end of the VFET. An isolation region is adjacent to the gate at a second end and opposing sides of the VFET and extends into the substrate. Contacts are formed including a lower source/drain contact (which is adjacent to the first end of the VFET and is self-aligned if the optional gate sidewall spacer is present) and a self-aligned gate contact (which extends into the isolation region at the second end of the VFET and contacts a side surface of the gate). Also disclosed are structures formed according to the methods.