Self-Aligned Gate Contacts With Insulator Cap Short Protection
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Solution Overview
Problem
As transistor gate pitches scale down, the likelihood of contact-to-gate shorts increases due to challenges in controlling registration and critical dimensions, leading to parasitic capacitance and performance degradation in MOS transistors.
Innovation Solution
The implementation of an insulator-cap layer atop the gate electrode and within the spacers of MOS transistors, which electrically isolates the metal gate electrode from the trench contact, reducing the risk of contact-to-gate shorts and parasitic capacitance by consuming a significant portion of the volume between spacers and withstanding etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate pitch is scaled down to increase transistor density, then productivity is improved, but manufacturing precision deteriorates due to difficulty in controlling registration and critical dimensions
Solution Approach 1:
An insulator cap layer is introduced as an intermediary element between the contact and gate electrode. This mediator provides a buffer zone that prevents direct contact even when registration is imperfect, thereby maintaining manufacturing feasibility while enabling scaled-down gate pitches for higher transistor density
Solution Approach 2:
The insulator cap layer is formed in advance before contact patterning. By pre-establishing this protective layer, the process creates a built-in safety margin that compensates for potential registration errors, allowing broader process windows and reducing the stringency of manufacturing precision requirements
2Reliability
If contact is formed closer to gate to reduce parasitic capacitance, then electrical performance is improved, but reliability deteriorates due to increased risk of contact-to-gate short
Solution Approach 1:
The insulator cap layer serves as a mediator that allows the contact to be positioned closer to the gate electrode without creating a short circuit. This enables reduction of parasitic capacitance by minimizing the distance between contact and gate, while the insulator cap maintains electrical isolation and ensures reliability
Solution Approach 2:
The insulator cap layer changes the electrical parameter (isolation) between contact and gate, allowing closer physical proximity without compromising electrical separation. This parameter change enables optimization of parasitic capacitance while maintaining short prevention
Data Source
AI summary
A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.