Self-Aligned Gate Contacts in Integrated Circuit Fabrication
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Solution Overview
Problem
Current methods for producing integrated circuits, such as double patterning and spacer patterning, face challenges in achieving precise alignment between gate zones and contacts, especially at smaller technology nodes, leading to inaccuracies in relative positions and compatibility issues with 'gate first' or 'gate last' approaches.
Innovation Solution
A method involving the production of insulating spacers and dielectric layers to align gate contacts self-aligned with gate zones, allowing for precise control of spacer thickness and position, enabling accurate alignment of active zone contacts with gate zones, suitable for both 'gate first' and 'gate last' approaches, and applicable to technology nodes below 22 nm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning or spacer patterning techniques are used to reduce pitch, then manufacturing precision of pitch is improved, but alignment precision between gate zones and contacts deteriorates due to mask removal inaccuracies
Solution Approach 1:
The gate zones themselves serve as the alignment reference for contact formation. By using the gate zones as etch stops during contact hole formation, the method eliminates the need for separate mask alignment between gate and contact layers, achieving self-aligned fabrication that resolves the alignment precision deterioration caused by conventional double patterning techniques
Solution Approach 2:
The gate zones are formed first with precise pitch using double patterning or spacer patterning, and then contact holes are formed subsequently using the gate zones as alignment references. This sequential approach with preliminary gate formation ensures that the pitch precision achieved in the first step is preserved and used as the foundation for accurate contact alignment
2Ease of manufacture
If conventional methods are used to define contact holes separately, then manufacturing simplicity is maintained, but alignment accuracy between contacts and gate zones deteriorates
Solution Approach 1:
The gate zones automatically serve as the alignment reference and etch stop for contact hole formation. The etching process for contacts is self-limited by the gate zone structure itself, eliminating the need for complex mask alignment procedures while maintaining high relative position accuracy between contacts and gate zones
3Measurement precision
If gate zones are partially etched to form gate contacts, then alignment precision is improved, but device complexity increases due to additional etching steps
Solution Approach 1:
The formation of gate zones and gate contacts is merged into a single integrated structure. The gate zones are partially etched to create both the gate region and the gate contact region in one continuous process flow, eliminating the need for separate formation steps and reducing overall process complexity while maintaining high alignment precision
Data Source
AI summary
A process for producing an integrated circuit on the surface of a substrate, the process including: producing a first layer, including active zones and insulating zones, on the surface of the substrate; producing gate zones on the surface of the first layer, the gate zones each being surrounded by insulating spacers; producing source/drain electrodes; producing a dielectric layer between the insulating spacers, the dielectric layer having an upper surface level with the upper surfaces of the gate zones; partially etching each gate zone so as to lower the upper surface of a first part of each gate zone; and depositing an insulating dielectric layer on the first parts of the gate zones.