Self-Aligned Gate Contacts With Spacer-Protecting Liner
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Solution Overview
Problem
The formation of gate contacts and source/drain contacts in densely packed gate structures of multi-gate devices, such as FinFETs and GAA transistors, poses challenges due to high overlay precision requirements, leading to issues like electrical shorts, leakage, and increased parasitic capacitance.
Innovation Solution
A method involving the deposition of a liner with different etching selectivity over gate spacers before forming self-aligned contact openings, which protects the spacers from damage during etching and reduces parasitic capacitance by using materials like silicon oxycarbonitride and zirconium oxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate contacts and source/drain contacts are formed in densely packed gate structures using conventional techniques, then manufacturing complexity is reduced, but overlay precision is insufficient leading to electrical shorts, leakage, and increased parasitic capacitance
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure and spacer features before the actual contact formation. The mandrel is deposited and patterned first, then spacers are formed around it, creating a pre-positioned alignment framework that guides subsequent contact hole formation. This preliminary structuring enables precise overlay without requiring high precision during the final contact etching step.
Solution Approach 2:
The patent introduces intermediary structures (mandrel and spacer) that mediate between the gate structure and the final contact. The mandrel serves as a temporary intermediary that defines the contact position, and the spacer acts as an intermediary that transfers this position information to the contact hole. These intermediaries decouple the alignment requirement from the final contact formation step.
2Reliability
If conventional contact formation techniques are used, then process simplicity is maintained, but gate spacer damage occurs leading to electrical shorts and increased parasitic capacitance
Solution Approach 1:
The patent applies preliminary anti-action by forming the spacer structure with appropriate material selection and dimensional design before contact hole formation. The spacer is made from materials and configured in dimensions that provide resistance against the etching process, preventing unwanted erosion or damage. This pre-engineered resistance counteracts the potential harmful effect of etching on the spacer.
Solution Approach 2:
The spacer structure serves a dual function: it defines the contact position and simultaneously protects the gate structure during contact formation. The spacer's geometry and material properties enable it to self-protect the underlying gate structure from etching damage while maintaining its position-defining function throughout the process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes damage to gate spacers, reducing electrical shorts and parasitic capacitance, thereby improving the reliability and performance of semiconductor devices.
Implementation Method 1
deposition of a liner with different etching selectivity over gate spacers before forming self-aligned contact openings, which protects the spacers from damage during etching
Implementation Method 2
reduces parasitic capacitance by using materials like silicon oxycarbonitride and zirconium oxide
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.