Self-Aligned Gate Contacts With Liner-Protected Spacers
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Solution Overview
Problem
The aggressive scaling down of semiconductor IC dimensions leads to densely spaced gate structures and source/drain contacts, posing challenges in forming gate contacts and source/drain contact vias due to high overlay precision requirements, which existing techniques have not adequately addressed, resulting in issues like electrical shorts, leakage, and increased parasitic capacitance.
Innovation Solution
The method involves depositing a liner over the gate structure and gate spacers with different etching selectivity than the self-aligned contact dielectric feature to prevent damage during the formation of gate contact openings, thereby reducing parasitic capacitance, electrical shorts, and leakage by protecting the gate spacers from etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If aggressive scaling down of IC dimensions is performed to improve production efficiency and lower costs, then productivity increases, but manufacturing precision requirements increase due to densely spaced gate structures and source/drain contacts
Solution Approach 1:
The gate spacer serves a dual function: it acts as a structural element defining the gate contact opening position, and simultaneously serves as a self-aligned mask during etching processes. The spacer's own structure provides the alignment reference, eliminating the need for separate alignment marks or additional lithography steps, thus achieving self-aligned fabrication that maintains precision while improving productivity
Solution Approach 2:
The gate spacer is formed in advance before the gate contact opening etch process. This preliminary formation establishes the precise location and dimensions of the gate contact opening, ensuring that subsequent etching is automatically aligned without requiring high overlay precision during the actual contact formation step
2Device complexity
If conventional etching processes are used without protective layers, then manufacturing complexity is reduced, but reliability deteriorates due to gate spacer damage causing electrical shorts, leakage, and increased parasitic capacitance
Solution Approach 1:
A liner layer is deposited conformally over the gate spacer and surrounding structures before the gate contact opening etch process. This liner acts as a protective cushion that prevents direct etching damage to the gate spacer, ensuring that even if etching conditions are not perfectly controlled, the spacer remains intact and electrical reliability is maintained
Solution Approach 2:
The liner layer serves as an intermediary between the etching process and the gate spacer. It absorbs the harsh etching conditions, allowing the etch to proceed through the dielectric material without directly attacking the gate spacer, thus protecting the spacer's integrity and preventing electrical failures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and electrical shorts by protecting the gate spacers and allows for more precise formation of gate contacts, enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
depositing a liner over the gate structure and gate spacers with different etching selectivity than the self-aligned contact dielectric feature to prevent damage during the formation of gate contact openings
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.