Self-aligned gate contacts via spacer-defined recess cavities
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor fabrication is the limited lateral area footprint for forming gate contacts, leading to interference with neighboring contacts, defects such as shadowing and shorting, and reduced cell routing flexibility due to strict design rules.
Innovation Solution
The method involves self-aligning gate contacts to gate spacers, allowing for minimal shift and electrical isolation, and combining this with self-aligned active area contacts, using sacrificial gate stacks and electrodes that can be replaced, with dielectric material cuts for precise patterning, enabling gate contacts within device channels without neighboring non-contacted gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate contacts are formed in the device channel to improve routing flexibility, then cell routing flexibility is improved, but interference with neighboring contacts occurs causing shadowing and shorting defects
Solution Approach 1:
Gate spacers are formed before gate contact patterning to pre-establish the lateral boundaries for contact formation. This preliminary structure defines the exact location where gate contacts can be formed without interfering with neighboring contacts, allowing contacts to be formed in the device channel while maintaining proper isolation.
Solution Approach 2:
Gate spacers act as an intermediary structure between the gate electrode and neighboring contacts. The spacers physically separate the gate contact region from adjacent active contacts, preventing shadowing and shorting defects while enabling flexible routing configurations.
2Reliability
If minimum design rules are applied to limit contact interference, then contact isolation is improved, but the lateral area footprint available for gate contacts is reduced
Solution Approach 1:
The gate spacer structure serves dual purposes: it provides electrical isolation between contacts while simultaneously defining the precise location for gate contact formation. This self-aligning approach eliminates the need for additional design rule margins, maximizing the lateral area footprint available for gate contacts within the device channel.
3Manufacturing precision
If self-aligned gate contacts are formed to improve placement precision, then manufacturing precision is improved, but process complexity increases due to additional spacer formation steps
Solution Approach 1:
The formation of gate spacers and gate contacts is merged into an integrated process sequence. The same spacer formation step that provides isolation also establishes the alignment reference for subsequent contact patterning, reducing the need for separate alignment operations and simplifying the overall fabrication process despite the additional spacer step.
Data Source
AI summary
The disclosed technology generally relates to semiconductor devices, and more specifically to electrical contacts to a transistor device, and a method of making such electrical contacts. In one aspect, a method of forming one or more self-aligned gate contacts in a semiconductor device includes providing a substrate having formed thereon at least one gate stack, where the gate stack includes a gate dielectric and a gate electrode formed over an active region in or on the substrate, and where the substrate further has formed thereon a spacer material coating lateral sides of the at least one gate stack. The method additionally includes selectively recessing the gate electrode of the at least one gate stack against the spacer material, thereby creating a first set of recess cavities. The method additionally includes filling the first set of recess cavities with a dielectric material gate cap. The method additionally includes etching at least one via above the at least one gate stack and through the dielectric material gate cap, where etching the at least one via comprises selectively etching against the spacer material, thereby exposing the gate electrode. The method further includes forming, in the at least one via, a gate contact electrically connecting the gate electrode.