Self-Aligned Gate Cut Structure for Open S/D Contacts
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Solution Overview
Problem
As semiconductor devices continue to scale down, the challenge of non-selective S/D contact etching poses a risk of gate shorting, and existing methods fail to selectively etch silicon nitride (SiN) in gate cut regions without affecting interlayer dielectric (ILD) regions, making it difficult to form open S/D contacts across gate cut regions.
Innovation Solution
A method is developed where a self-aligned cap (SAC) is formed over field effect transistor (FET) structures, a gate cut etch mask is patterned, and material is etched deeper than the gate bottom, with SiN liner deposited only on gate and spacer sidewalls, not on ILD regions, allowing the remainder of the opening to be filled with SiO2, ensuring SiN is present only next to the gate and spacers but not on ILD regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If non-selective S/D contact etching is performed, then etching process is simple, but gate shorting risk increases
Solution Approach 1:
The patent applies local quality by making the etching process selective to different regions. The SAC cap structure creates different etch resistance in gate regions versus ILD regions, allowing the etch to selectively remove material in ILD regions while preserving gate structures, thus preventing gate shorting while maintaining process simplicity
2Manufacturing precision
If SiN liner is deposited in all regions, then liner coverage is complete, but ILD region contamination occurs
Solution Approach 1:
The patent uses local quality by making the SiN liner deposition selective to gate and spacer regions only. The SAC cap structure prevents liner deposition in ILD regions through self-alignment, ensuring complete liner coverage where needed while avoiding contamination in ILD regions
Solution Approach 2:
The SAC cap structure performs self-service by automatically preventing SiN liner deposition in ILD regions. The cap's geometry and positioning cause the liner deposition process to self-align and self-limit, depositing liner only in gate and spacer regions without requiring additional masking or control steps
3Manufacturing precision
If etching depth exceeds gate bottom, then opening is formed properly, but gate structure damage occurs
Solution Approach 1:
The patent applies local quality by creating different etch resistance in different regions. The SAC cap provides protective coverage over gate regions during etching, allowing the etch to proceed to the required depth in ILD regions while the cap protects the gate structure from damage
Solution Approach 2:
The SAC cap structure provides beforehand cushioning by being formed prior to the etching process. This cap structure acts as a protective layer that cushions and protects the gate structure during the deep etching process, preventing gate damage while allowing proper opening formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables post RMG gate cut compatibility with SAC processing by preventing SiN liner deposition in ILD regions, thus allowing for open S/D contacts across gate cut regions without risking gate shorting, enhancing the fabrication process for semiconductor devices.
Implementation Method 1
patterning a gate cut etch mask for opening gates
Implementation Method 2
etching material exposed by the gate cut etch mask to a depth deeper than a bottom of the gates to form an opening
Implementation Method 3
depositing a liner material on sidewalls of the gates and the spacers but not on the ILD under the overhang in the opening
Data Source
AI summary
A semiconductor device is provided and includes gate regions interleaved between interlayer dielectric (ILD) regions, field effect transistor (FET) structures extending across the gate regions and the ILD regions, source and drain (S/D) regions, shared between the gate regions, at exterior ones of the ILD regions, dielectric material between the FET structures and bisecting the gate regions and the ILD regions, liner material and contacts. The liner material is disposed on opposite sides of the dielectric material in the gate regions and not in the ILD regions. The contacts are formed about the FET structures in the exterior ones of the ILD regions and across the dielectric material at an interior one of the ILD regions.