Self-Aligned FinFET Gate Cut Features for Tighter Gate Isolation
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Solution Overview
Problem
The challenge in semiconductor integrated circuit manufacturing lies in achieving precise and uniform cutting of gate electrodes in FinFETs, particularly in reducing alignment errors and spacing between fins, which affects yield and circuit area.
Innovation Solution
A self-aligned process is employed to form insulating cut features between device fins using a spacer material, ensuring accurate alignment and reduced spacing, and subsequent etching techniques to create electrically isolated gates with precise cut feature widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate cutting processes are used to electrically isolate gates, then gate isolation is achieved, but alignment errors increase and spacing between fins must be larger
Solution Approach 1:
The patent applies preliminary action by forming the cut feature between fins before depositing the gate material. This self-aligned approach ensures that the gate automatically aligns with the fin structure, eliminating alignment errors that occur when cutting gates after formation. The cut feature is created as a placeholder that guides subsequent gate deposition, ensuring precise alignment without requiring additional alignment steps.
Solution Approach 2:
The patent implements self-service through the self-aligned process where the cut feature between fins serves multiple functions: it provides electrical isolation, defines the gate position, and guides gate material deposition. The structure serves itself by using the fin spacing and cut feature geometry to automatically establish precise gate alignment, eliminating the need for separate alignment procedures and reducing manufacturing complexity.
2Reliability
If conventional gate cutting processes are used, then gate isolation is achieved, but circuit area increases due to larger spacing requirements
Solution Approach 1:
By forming the cut feature between fins before gate deposition, the patent enables tighter fin spacing while maintaining gate isolation. The preliminary cut feature acts as a template that allows subsequent gate material to be deposited precisely where needed, reducing the spacing buffer required in conventional processes and thereby reducing overall circuit area.
Solution Approach 2:
The self-aligned cut feature structure serves multiple functions simultaneously - providing electrical isolation, defining gate boundaries, and enabling tighter packing of fins. This multi-functionality reduces the total area required for gate isolation structures compared to conventional methods that require separate isolation regions and larger spacing margins.
3Productivity
If device sizes are reduced to increase density, then functional density increases, but the ability to perform cut processes deteriorates
Solution Approach 1:
The patent addresses the challenge of scaling by performing the cut feature formation at an earlier stage when structures are larger and easier to manufacture. The preliminary cut feature is created between fins before any gate materials are deposited, allowing use of less aggressive etching conditions and better process control. This early formation maintains cut process capability even as final device dimensions are reduced to increase density.
Solution Approach 2:
The self-aligned nature of the cut feature process provides inherent process control that becomes increasingly valuable at smaller dimensions. The cut feature automatically defines the gate position and dimensions, reducing the impact of variability and making the manufacturing process more robust as device sizes shrink. This self-service mechanism maintains ease of manufacture while enabling higher functional density.
Data Source
AI summary
Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.