Self-Aligned Gate-Cut Structure for Stacked Transistor Spacing
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Solution Overview
Problem
As transistor sizes in integrated circuit devices continue to shrink, the challenge of forming gate-cuts between transistor structures without misalignment becomes significant, potentially damaging adjacent transistors and affecting their performance.
Innovation Solution
The implementation of self-aligned gate-cuts with sloped sidewalls, formed on a sacrificial spacer that maintains adequate spacing from adjacent transistors, addresses the misalignment issue and prevents damage to the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor sizes are shrunk to down-scale logic elements, then transistor density is increased, but misalignment risk during gate-cut formation increases, potentially damaging adjacent transistors
Solution Approach 1:
A sacrificial spacer layer is introduced as an intermediary element between the gate-cut and the transistor structures. This spacer serves as a protective mediator that maintains precise spacing during the gate-cut formation process, preventing direct contact and potential damage to the scaled-down transistor structures while enabling accurate gate-cut placement.
Solution Approach 2:
The sacrificial spacer is formed in advance before the gate-cut is created. This preliminary action establishes the precise spacing geometry needed for accurate gate-cut alignment, allowing the gate-cut to be formed with correct positioning relative to the transistor structures without risking misalignment or damage during the actual cutting process.
2Area of stationary object
If gate-cuts are formed closer to transistor structures to increase density, then area is reduced, but the risk of damaging transistors during gate-cut formation increases
Solution Approach 1:
The sacrificial spacer acts as a protective intermediary that enables the gate-cut to be positioned closer to the transistor structures without causing damage. The spacer maintains a controlled gap between the gate-cut and the transistor, allowing minimal spacing for area reduction while preventing harmful contact during formation.
Solution Approach 2:
The sacrificial spacer provides beforehand cushioning by being positioned between the gate-cut and the transistor structures prior to gate-cut formation. This cushioning layer absorbs or prevents potential damage during the gate-cut process, allowing the gate-cut to be formed closer to the transistors with reduced damage risk.
3Ease of manufacture
If conventional gate-cuts are used without self-alignment, then manufacturing process is simpler, but misalignment occurs that affects transistor performance
Solution Approach 1:
The sacrificial spacer serves as a self-aligning intermediary that guides the gate-cut formation process. By forming the gate-cut relative to the spacer rather than directly relative to the transistor structures, the process achieves automatic alignment, maintaining manufacturing simplicity while ensuring consistent positioning and reliable transistor performance.
Solution Approach 2:
The sacrificial spacer enables self-alignment of the gate-cut to the transistor structures. The spacer's position relative to the transistors automatically defines the correct gate-cut location, allowing the structure to self-align during formation without requiring complex external alignment processes, thus maintaining ease of manufacture while improving reliability.
Data Source
AI summary
Transistor devices are provided. A transistor device includes a substrate and a transistor stack on the substrate. The transistor stack includes a lower transistor and an upper transistor that is on top of the lower transistor. Moreover, the transistor device includes a gate-cut on the substrate, adjacent the transistor stack. The gate-cut has a first sloped sidewall and a second sloped sidewall that is opposite the first sloped sidewall. Related methods of forming transistor devices are also provided.