Self-Aligned Metal Gate Cutting for Dense Multigate Layouts
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Solution Overview
Problem
Non-self-aligned gate cutting techniques in multigate devices hinder dense packing of IC features, leading to increased spacing between active device areas and reduced pattern density, which affects the performance and efficiency of advanced IC technology nodes.
Innovation Solution
A self-aligned gate cutting technique is employed to reduce spacing between active device areas, allowing for smaller metal gate and source/drain feature dimensions, thereby increasing pattern density and reducing parasitic capacitance, while using asymmetric gate profiles and dielectric fins for electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-self-aligned gate cutting techniques are used to isolate gates of different GAA devices, then gate isolation is achieved, but spacing between active device areas increases and pattern density decreases
Solution Approach 1:
The gate structure itself serves as the alignment reference for cutting isolation trenches. The self-aligned process uses the gate's physical position to define the trench location, eliminating the need for separate alignment steps and achieving both isolation and minimal spacing simultaneously
Solution Approach 2:
The gate structure is formed first as a reference feature before the isolation trenches are etched. This preliminary formation of the gate allows subsequent trench etching to be precisely positioned relative to the gate, ensuring proper isolation while minimizing spacing
2Reliability
If non-self-aligned gate cutting techniques are used, then gate isolation is achieved, but pattern density is reduced
Solution Approach 1:
The gate structure serves as its own alignment reference, enabling the cutting process to automatically achieve correct positioning without additional alignment steps. This self-aligning mechanism maximizes pattern density by eliminating extra spacing requirements
Solution Approach 2:
By forming the gate structure first as a preliminary step, the subsequent isolation trench etching can be precisely positioned relative to the gate, achieving both proper isolation and high pattern density in the final device layout
Data Source
AI summary
Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.