Self-aligned gate edge finFET devices for transistor density
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Solution Overview
Problem
Conventional methods for fabricating multi-gate transistors face challenges in scaling due to limitations in lithographic patterning, leading to increased gate capacitance and reduced transistor density, as they require extra endcap length for mask registration error, which degrades performance and increases dynamic energy consumption.
Innovation Solution
The implementation of a self-aligned gate endcap (SAGE) process that uses disposable spacers to determine gate and trench contact endcap dimensions, eliminating the need for extra endcap length to account for mask mis-registration, and allowing for independent optimization of fin-height and transistor layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic patterning is used to fabricate multi-gate transistors, then mask registration error is accommodated by adding extra endcap length, but transistor layout area increases and transistor density decreases
Solution Approach 1:
The gate edge isolation structure serves itself as the alignment reference for forming the gate electrode. The disposable spacer is formed based on the gate edge isolation structure, and the gate electrode is subsequently formed self-aligned to the spacer, eliminating the need for separate mask alignment steps and extra endcap length for registration error
Solution Approach 2:
The gate edge isolation structure and disposable spacer are formed in advance before the gate electrode formation. The disposable spacer pre-defines the exact position and dimension of the gate endcap, so when the gate electrode is formed later, it automatically aligns without requiring additional mask steps or extra length for registration tolerance
2Reliability
If extra endcap length is added for mask registration error, then manufacturing robustness improves, but gate capacitance increases and performance degrades
Solution Approach 1:
The gate edge isolation structure serves as the self-aligned reference for the disposable spacer and gate electrode formation. This self-service approach eliminates mask registration errors entirely, providing robustness without requiring extra endcap length, thereby reducing gate capacitance and dynamic energy consumption
Solution Approach 2:
The invention extracts and eliminates the unnecessary extra endcap length that was previously added to accommodate mask registration errors. By using the self-aligned disposable spacer process, the registration robustness is achieved through process design rather than dimensional compensation, removing the harmful extra length that increases gate capacitance
3Length of moving object
If conventional patterning processes are used, then feature size can be reduced, but spacing between features must be increased to accommodate registration error
Solution Approach 1:
The disposable spacer process makes the feature spacing independent of mask registration error. The spacer is formed self-aligned to the gate edge isolation structure with a fixed thickness that defines the gate endcap position, allowing features to be placed closer together without increasing spacing for registration tolerance
Solution Approach 2:
The disposable spacer is formed in advance as a self-aligned structure that pre-determines the exact spacing and position of subsequent gate electrodes. This preliminary action eliminates the need for increased spacing between features, as the self-aligned process inherently compensates for any registration variations
Data Source
AI summary
Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.