Self-Aligned Gate Endcap Architecture for FinFET Scaling
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to constraints in lithographic processes, leading to trade-offs between feature dimension and spacing, and increased gate capacitance, which affects performance and energy consumption.
Innovation Solution
The implementation of self-aligned gate endcap (SAGE) architectures, where disposable spacers determine gate and contact overlap dimensions, eliminating the need for extra endcap length to account for mask registration errors, and allowing for self-aligned gate and trench contact endcap overlap without lithographic patterning at certain stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithographic processes are used to pattern transistor features, then feature dimensions can be reduced, but spacing between features must be increased due to mask registration errors
Solution Approach 1:
The gate endcap structures are formed using a self-aligned process where the endcap isolation structures are deposited and patterned to automatically align with the gate structures. This self-alignment eliminates the need for additional spacing that would otherwise be required to accommodate mask registration errors in conventional lithographic processes, thereby reducing the spacing between features while maintaining manufacturing precision.
2Manufacturing precision
If gate endcap structures are formed with additional length to account for mask registration errors, then manufacturing precision is maintained, but device capacitance increases
Solution Approach 1:
The self-aligned gate endcap process forms endcap isolation structures that automatically align with gate structures through conformal deposition and selective etching. This eliminates the need to add extra endcap length for mask registration tolerance, thereby reducing parasitic gate capacitance while maintaining manufacturing precision through the self-alignment mechanism.
Solution Approach 2:
The invention extracts and eliminates the unnecessary portion of gate endcap structures that would otherwise be added to compensate for mask registration errors. By removing this excess material through the self-aligned process, the parasitic capacitance is reduced while the essential alignment function is preserved through the self-aligned formation mechanism.
3Quantity of substance
If conventional multi-gate transistor fabrication is used, then device density can be increased, but lithographic constraints become overwhelming
Solution Approach 1:
The self-aligned gate endcap process simplifies the lithographic requirements by using self-alignment mechanisms instead of relying on precise mask registration. This allows for increased device density to be achieved without overwhelming lithographic constraints, as the self-aligned process is less sensitive to lithographic variations and enables tighter feature spacing.
Data Source
AI summary
Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.