Self-Aligned Gate Endcap Layout for Dense GAA Transistors
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Solution Overview
Problem
Conventional lithographic processes struggle to scale gate endcap and trench contact endcap regions in semiconductor devices, leading to increased gate capacitance and degraded performance due to mask registration errors and limited diffusion spacing.
Innovation Solution
Implementing a self-aligned gate endcap (SAGE) architecture with gate-all-around devices, where gate and trench contact endcaps are self-aligned to semiconductor fins or nanowires without requiring extra length for mask mis-registration, using disposable spacers to define endcap dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern gate endcap and trench contact endcap regions, then mask registration errors and limited diffusion spacing occur, but device density and performance are degraded
Solution Approach 1:
The gate endcap and trench contact endcap regions are self-aligned to the semiconductor fin or nanowire, eliminating the need for separate lithographic patterning steps. The self-alignment mechanism inherently prevents mask registration errors while enabling tighter diffusion spacing, thus resolving the contradiction between manufacturing precision and device density.
Solution Approach 2:
The gate endcap and trench contact endcap regions are formed simultaneously with the gate structure in a preliminary fabrication step, rather than requiring subsequent separate patterning steps. This preliminary action eliminates mask registration errors and enables tighter diffusion spacing, improving both manufacturing precision and device density.
2Manufacturing precision
If gate endcap and trench contact endcap regions are not self-aligned, then mask registration errors increase, but gate capacitance increases and performance degrades
Solution Approach 1:
The gate endcap and trench contact endcap regions are self-aligned to the semiconductor fin or nanowire, eliminating the need for separate lithographic patterning steps. The self-alignment mechanism inherently prevents mask registration errors while enabling tighter diffusion spacing, thus resolving the contradiction between manufacturing precision and device density.
Solution Approach 2:
The gate endcap and trench contact endcap regions are formed simultaneously with the gate structure in a preliminary fabrication step, rather than requiring subsequent separate patterning steps. This preliminary action eliminates mask registration errors and enables tighter diffusion spacing, improving both manufacturing precision and device density.
3Manufacturing precision
If diffusion spacing is increased to accommodate mask registration tolerances, then manufacturing precision improves, but device layout density decreases
Solution Approach 1:
The gate endcap and trench contact endcap regions are self-aligned to the semiconductor fin or nanowire, eliminating the need for separate lithographic patterning steps. The self-alignment mechanism inherently prevents mask registration errors while enabling tighter diffusion spacing, thus resolving the contradiction between manufacturing precision and device density.
Solution Approach 2:
The gate endcap and trench contact endcap regions are formed simultaneously with the gate structure in a preliminary fabrication step, rather than requiring subsequent separate patterning steps. This preliminary action eliminates mask registration errors and enables tighter diffusion spacing, improving both manufacturing precision and device density.
Data Source
AI summary
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.