Self-Aligned Gate Endcap Architecture for Transistor Scaling
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in scaling down multi-gate transistors due to limitations in lithographic patterning, leading to increased gate capacitance and reduced transistor performance, particularly in achieving tight diffusion end-to-end spacing without compromising mask registration accuracy.
Innovation Solution
The implementation of unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, which eliminates the need for extra endcap length to account for mask mis-registration by using disposable spacers to self-align gate and trench contact endcaps to semiconductor fins, thereby reducing device variability and improving electrical parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic patterning is used to pattern transistor features, then mask registration accuracy can be maintained, but diffusion end-to-end spacing cannot be reduced sufficiently
Solution Approach 1:
The gate endcap structure performs dual functions: it serves as both the gate electrode extension and the alignment reference for trench contact patterning. The trench contact is self-aligned to the gate endcap through conformal spacer formation, eliminating the need for separate mask alignment steps and enabling reduced diffusion spacing while maintaining registration accuracy.
Solution Approach 2:
The gate endcap structure is designed to fulfill multiple roles: it extends the gate electrode for electrical function, provides the alignment reference for trench contact positioning, and serves as the template for spacer formation. This multi-functionality consolidates multiple patterning steps into fewer operations, enabling tighter spacing.
2Manufacturing precision
If extra endcap length is added to account for mask mis-registration, then mask registration tolerance is improved, but device variability increases
Solution Approach 1:
The structure uses itself as the alignment reference - the gate endcap serves as the template for forming the trench contact alignment spacer. This self-aligned approach eliminates dependence on mask-to-mask registration, removing the need for extra endcap length as a tolerance buffer while achieving precise alignment and reducing device variability.
Solution Approach 2:
The gate endcap structure is formed first, establishing the precise geometric reference before trench contact patterning begins. The conformal spacer is then deposited conformally on the gate endcap, automatically positioning the trench contact with high precision. This preliminary establishment of the reference structure eliminates subsequent alignment variability.
3Ease of manufacture
If lithographic patterning is used for all stages, then manufacturing process completeness is maintained, but manufacturing complexity increases
Solution Approach 1:
The patent extracts the alignment reference function from the lithographic patterning process and embeds it in the gate endcap structure itself. By removing the need for separate alignment markers and reducing the number of lithographic steps, the process complexity is reduced while maintaining completeness through the self-aligned spacer formation approach.
Solution Approach 2:
The conformal spacer acts as an intermediary structure that transfers the alignment information from the gate endcap to the trench contact. This intermediary enables precise alignment without requiring direct lithographic patterning of the trench contact, simplifying the overall patterning process while maintaining manufacturing completeness.
Data Source
AI summary
Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.