Self-Aligned Gate Endcap Layout for Tighter FinFET Spacing
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in scaling down multi-gate transistors due to limitations in lithographic processes, leading to trade-offs between feature size and spacing, which affect transistor density and performance.
Innovation Solution
The implementation of self-aligned gate endcap (SAGE) architectures with reduced or removed caps, utilizing a high-k dielectric material etch process and disposable spacers to self-align gate and trench contact endcaps, eliminating the need for extra endcap length to account for mask registration errors and reducing lithographic patterning requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern transistor features, then manufacturing simplicity is maintained, but the critical dimension and spacing between features cannot be sufficiently reduced
Solution Approach 1:
The gate endcap isolation structure serves itself as the alignment reference for forming trench contact endcaps. The disposable spacers self-align to the gate endcap isolation structure, eliminating the need for separate lithographic alignment steps and mask registration processes. This self-service mechanism enables reduced spacing while avoiding increased process complexity.
Solution Approach 2:
Disposable spacers act as intermediaries between the gate endcap isolation structure and the trench contact endcaps. These spacers are formed conformally on the sidewalls of the gate endcap isolation structure and serve as temporary alignment references that are later removed, enabling precise spacing without complex lithography.
2Reliability
If extra endcap length is added to account for mask registration errors, then manufacturing robustness is improved, but transistor layout density decreases
Solution Approach 1:
The gate endcap isolation structure and disposable spacers form a self-aligning system that eliminates mask registration errors entirely. Since the spacers are formed conformally on the isolation structure sidewalls rather than through separate lithographic steps, there is no mask alignment required, and thus no need for extra endcap length for tolerance compensation.
Solution Approach 2:
The invention extracts and removes the mask registration step from the fabrication process by using self-aligned spacer formation. This eliminates the source of registration errors, allowing endcaps to be formed with minimal length without compromising manufacturing robustness.
3Stability of the object's composition
If traditional gate endcap structures with full caps are used, then structural stability is maintained, but gate capacitance and dynamic energy consumption increase
Solution Approach 1:
The invention extracts and removes the high-k dielectric cap layer from the gate endcap isolation structure after the trench contact endcaps have been formed. This removal eliminates unnecessary capacitance between the gate and surrounding structures, reducing dynamic energy consumption while the underlying lower-k dielectric wall maintains the structural stability during fabrication.
Solution Approach 2:
The gate endcap isolation structure has different dielectric properties at different locations: a lower-k dielectric wall for structural stability and a higher-k dielectric cap that is selectively removed to reduce capacitance. This local differentiation of material properties optimizes both structural integrity and electrical performance.
Data Source
AI summary
Self-aligned gate endcap (SAGE) architectures with reduced or removed caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with reduced or removed caps, are described. In an example, an integrated circuit structure includes a first gate electrode over a first semiconductor fin. A second gate electrode is over a second semiconductor fin. A gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. A local interconnect is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.