Self-aligned Gate Endcap Architecture for Transistor Density
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits leads to challenges in lithographic processes, particularly in achieving precise patterning of gate and contact endcaps, resulting in increased capacitance and switching delays due to larger footprints and the need for additional metal layers, which compromises transistor density and performance.
Innovation Solution
The implementation of self-aligned gate endcap (SAGE) architectures with local interconnects, which eliminate the need for extra mask registration and lithographic patterning, allowing for self-aligned gate and trench contact endcaps and interconnects, thereby reducing capacitance and enabling area scaling without additional mask operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic patterning is used for gate and contact endcaps, then precise patterning can be achieved, but the footprint increases and additional metal layers are required, increasing capacitance and switching delays
Solution Approach 1:
The patent merges the gate endcap and contact endcap patterning into a single self-aligned process. The gate endcap is formed using the gate mandrel, and the contact endcap is formed using the gate endcap as a mask, eliminating the need for separate critical masks and reducing the overall footprint while maintaining patterning precision.
Solution Approach 2:
The gate endcap structure serves dual purposes: it acts as both the gate electrode extension and the mask for forming the contact endcap. This self-aligned approach eliminates the need for additional mask operations and reduces the footprint by avoiding separate patterning steps.
2Area of moving object
If transistor size is reduced to increase density, then capacity increases, but lithographic constraints become overwhelming and spacing between features must increase
Solution Approach 1:
The self-aligned gate endcap process eliminates the need for additional mask operations. The gate endcap structure automatically serves as the mask for contact endcap formation, removing critical mask registration requirements and enabling smaller transistor sizes without compromising patterning precision.
Solution Approach 2:
The patent transitions from planar patterning to a self-aligned three-dimensional approach where the gate endcap structure itself provides the alignment reference. This dimensional shift eliminates lithographic spacing constraints by using the structure's geometry rather than mask patterns to define feature positions.
3Manufacturing precision
If additional mask operations are performed for endcap patterning, then precise alignment can be achieved, but the total mask count increases and dynamic energy consumption increases
Solution Approach 1:
The gate endcap structure serves as its own mask for contact endcap formation. This self-aligned approach eliminates the need for separate critical masks, reducing the total mask count and associated dynamic energy consumption while maintaining precise alignment through the physical geometry of the gate endcap itself.
Data Source
AI summary
Self-aligned gate endcap (SAGE) architectures having local interconnects, and methods of fabricating SAGE architectures having local interconnects, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin, and a second gate structure over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between and in contact with the first and second gate structures. A local gate interconnect is between the gate plug and the gate endcap isolation structure, the local gate interconnect in contact with the first and second gate structures.